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1. 发明授权

US07516427B2 Input capacitance characterization method in IP library 失效
标题翻译： IP库中的输入电容表征方法
公开(公告)号：US07516427B2
公开(公告)日：2009-04-07
申请号：US11197820
申请日：2005-08-05
申请人： Peter H. Chen , Han-Chi Liu , Chih-Yang Peng , Jyh-Herng Wang , Chia-Nan Hong
发明人： Peter H. Chen , Han-Chi Liu , Chih-Yang Peng , Jyh-Herng Wang , Chia-Nan Hong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.
摘要翻译：提供了一个用于表征知识产权（知识产权）组件的方法。通过跳过模拟引脚和特殊IO引脚可识别数字引脚。响应于输入引脚的连接，IP组件的前两层被分类。提取IP组件的部分电路进行仿真。生成IP库的三个角落。因此，模拟IP组件的输入电容。

2. 发明申请

US20070033547A1 Input capacitance characterization method in IP library 失效
标题翻译： IP库中的输入电容表征方法
公开(公告)号：US20070033547A1
公开(公告)日：2007-02-08
申请号：US11197820
申请日：2005-08-05
申请人： Peter Chen , Han-Chi Liu , Chih-Yang Peng , Jyh-Herng Wang , Chia-Nan Hong
发明人： Peter Chen , Han-Chi Liu , Chih-Yang Peng , Jyh-Herng Wang , Chia-Nan Hong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.
摘要翻译：提供了一个用于表征知识产权（知识产权）组件的方法。通过跳过模拟引脚和特殊IO引脚可识别数字引脚。响应于输入引脚的连接，将IP组件的前两层分类。提取IP组件的部分电路进行仿真。生成IP库的三个角落。因此，模拟IP组件的输入电容。

3. 发明申请

US20080246502A1 SEMICONDUCTOR DEVICE FOR TESTING SEMICONDUCTOR PROCESS AND METHOD THEREOF 失效
标题翻译：用于测试半导体工艺的半导体器件及其方法
公开(公告)号：US20080246502A1
公开(公告)日：2008-10-09
申请号：US11695610
申请日：2007-04-03
申请人： Chia-Nan Hong , Yi-Hua Chang , Chin-Yi Chang
发明人： Chia-Nan Hong , Yi-Hua Chang , Chin-Yi Chang
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , G01R31/2831
摘要： A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing group includes a first testing block and a second testing. The first testing block includes: a first input node; a first output node; a plurality of first selecting nodes; a first reference device, coupled to the first input node and the first output node; and a first target device, coupled to the first selecting nodes and the first output node. The second testing block includes: a second input node; a second output node; a plurality of second selecting nodes; a second reference device, coupled to the second input node and the second output node; and a second target device, coupled to the second selecting nodes and the second output node.
摘要翻译：公开了一种用于测试半导体器件的半导体器件，该半导体器件用于制造半导体器件。半导体器件至少包括测试组。测试组包括第一个测试块和第二个测试。第一测试块包括：第一输入节点; 第一输出节点; 多个第一选择节点; 耦合到第一输入节点和第一输出节点的第一参考装置; 以及耦合到所述第一选择节点和所述第一输出节点的第一目标设备。第二测试块包括：第二输入节点; 第二输出节点; 多个第二选择节点; 耦合到所述第二输入节点和所述第二输出节点的第二参考装置; 以及耦合到所述第二选择节点和所述第二输出节点的第二目标设备。

4. 发明授权

US07603598B2 Semiconductor device for testing semiconductor process and method thereof 失效
标题翻译：用于半导体工艺测试的半导体器件及其方法
公开(公告)号：US07603598B2
公开(公告)日：2009-10-13
申请号：US11695610
申请日：2007-04-03
申请人： Chia-Nan Hong , Yi-Hua Chang , Chin-Yi Chang
发明人： Chia-Nan Hong , Yi-Hua Chang , Chin-Yi Chang
IPC分类号： G01R31/28
CPC分类号： G01R31/2884 , G01R31/2831
摘要： A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing group includes a first testing block and a second testing block. The first testing block includes: a first input node; a first output node; a plurality of first selecting nodes; a first reference device, coupled to the first input node and the first output node; and a first target device, coupled to the first selecting nodes and the first output node. The second testing block includes: a second input node; a second output node; a plurality of second selecting nodes; a second reference device, coupled to the second input node and the second output node; and a second target device, coupled to the second selecting nodes and the second output node.
摘要翻译：公开了一种用于测试半导体器件的半导体器件，该半导体器件用于制造半导体器件半导体器件至少包括测试组。测试组包括第一测试块和第二测试块。第一测试块包括：第一输入节点; 第一输出节点; 多个第一选择节点; 耦合到第一输入节点和第一输出节点的第一参考装置; 以及耦合到所述第一选择节点和所述第一输出节点的第一目标设备。第二测试块包括：第二输入节点; 第二输出节点; 多个第二选择节点; 耦合到所述第二输入节点和所述第二输出节点的第二参考装置; 以及耦合到所述第二选择节点和所述第二输出节点的第二目标设备。

5. 发明申请

US20090014801A1 DECOUPLING CAPACITOR CIRCUIT AND LAYOUT FOR LEAKAGE CURRENT REDUCTION AND ESD PROTECTION IMPROVEMENT 审中-公开
标题翻译：用于泄漏电流降低和ESD保护改进的解耦电容器和布局
公开(公告)号：US20090014801A1
公开(公告)日：2009-01-15
申请号：US11775584
申请日：2007-07-10
申请人： Wang-Jin Chen , Chia-Nan Hong
发明人： Wang-Jin Chen , Chia-Nan Hong
IPC分类号： H01L23/62
CPC分类号： H01L27/0266
摘要： In order to reduce the leakage current and increase the ESD protection performance, several MOS capacitors are serially connected. The E field between the gate and the source/drain of the MOS transistor is lowered and so is the gate leakage current. Besides, because the ESD voltage is distributed on the gates of the MOS capacitors, the MOS capacitors have good ESD protection performance.
摘要翻译：为了降低漏电流并增加ESD保护性能，几个MOS电容串联。 MOS晶体管的栅极和源极/漏极之间的E场降低，栅极漏电流也降低。此外，由于ESD电压分布在MOS电容器的栅极上，所以MOS电容器具有良好的ESD保护性能。

6. 发明授权

US07078930B2 Integrated circuit chip with high area utilization rate 失效
标题翻译：集成电路芯片具有较高的面积利用率
公开(公告)号：US07078930B2
公开(公告)日：2006-07-18
申请号：US10907608
申请日：2005-04-07
申请人： Tin-Hao Lin , Chia-Nan Hong
发明人： Tin-Hao Lin , Chia-Nan Hong
IPC分类号： H03K19/00
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip with a high area utilization rate includes: a plurality of logic circuits in a logic area; a first input and output circuit near a first side of the logic area for exchanging signals with the logic circuit; a second input and output circuit near a second side of the logic area for exchanging signals with the logic circuit; a plurality of first probe pads coupled to the first and the second input and output circuits for inputting or outputting signals to the first and the second input and output circuits; a corner cell comprising a plurality of wires coupled to the first and the second input and output circuits for exchanging signals between the first and the second input and output circuits; and a first process monitor circuit formed in the corner cell for monitoring a semiconductor process of the integrated circuit chip.
摘要翻译：具有高面积利用率的集成电路芯片包括：逻辑区域中的多个逻辑电路; 靠近用于与逻辑电路交换信号的逻辑区域的第一侧的第一输入和输出电路; 靠近逻辑区域的第二侧的第二输入和输出电路，用于与逻辑电路交换信号; 耦合到第一和第二输入和输出电路的多个第一探针焊盘，用于向第一和第二输入和输出电路输入或输出信号; 角电池包括耦合到第一和第二输入和输出电路的多条导线，用于在第一和第二输入和输出电路之间交换信号; 以及形成在角电池中的用于监视集成电路芯片的半导体工艺的第一处理监视电路。

7. 发明申请

US20060106907A1 Method of analyzing correlations among four variables in two-dimension configuration and computer accessible medium 审中-公开
标题翻译：分析二维配置和计算机可访问介质中四个变量之间的相关性的方法
公开(公告)号：US20060106907A1
公开(公告)日：2006-05-18
申请号：US10992028
申请日：2004-11-17
申请人： Sau-Ann Su , Chia-Nan Hong
发明人： Sau-Ann Su , Chia-Nan Hong
IPC分类号： G06F17/15
CPC分类号： G06K9/6253
摘要： A method of analyzing a correlation among four variables in a two dimensions configuration and a computer accessible medium for storing a program thereof are provided. The method comprises providing a plurality of data comprising a first variable, a second variable, a third variable and a fourth variable. The first to the fourth variables have correlations. Then the data are marked in the two-dimension configuration according to the first and the second variables. The group correlation is marked according to the third variable. The character of the fourth variable is shown by a predetermined method in the two-dimension configuration according to the fourth variable.
摘要翻译：提供了一种分析二维配置中的四个变量与用于存储其程序的计算机可访问介质之间的相关性的方法。该方法包括提供包括第一变量，第二变量，第三变量和第四变量的多个数据。第一到第四个变量都有相关性。然后根据第一个和第二个变量在二维配置中标记数据。组相关性根据第三个变量进行标记。根据第四变量的二维构造中的第四变量的字符由预定方法示出。

8. 发明申请

US20060071685A1 Integrated Circuit Chip With High Area Utilization Rate 失效
标题翻译：高面积利用率的集成电路芯片
公开(公告)号：US20060071685A1
公开(公告)日：2006-04-06
申请号：US10907608
申请日：2005-04-07
申请人： Tin-Hao Lin , Chia-Nan Hong
发明人： Tin-Hao Lin , Chia-Nan Hong
IPC分类号： H03K19/173
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip with a high area utilization rate includes: a plurality of logic circuits in a logic area; a first input and output circuit near a first side of the logic area for exchanging signals with the logic circuit; a second input and output circuit near a second side of the logic area for exchanging signals with the logic circuit; a plurality of first probe pads coupled to the first and the second input and output circuits for inputting or outputting signals to the first and the second input and output circuits; a corner cell comprising a plurality of wires coupled to the first and the second input and output circuits for exchanging signals between the first and the second input and output circuits; and a first process monitor circuit formed in the corner cell for monitoring a semiconductor process of the integrated circuit chip.
摘要翻译：具有高面积利用率的集成电路芯片包括：逻辑区域中的多个逻辑电路; 靠近用于与逻辑电路交换信号的逻辑区域的第一侧的第一输入和输出电路; 靠近逻辑区域的第二侧的第二输入和输出电路，用于与逻辑电路交换信号; 耦合到第一和第二输入和输出电路的多个第一探针焊盘，用于向第一和第二输入和输出电路输入或输出信号; 角电池包括耦合到第一和第二输入和输出电路的多条导线，用于在第一和第二输入和输出电路之间交换信号; 以及形成在角电池中的用于监视集成电路芯片的半导体工艺的第一处理监视电路。

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