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1. 发明授权

US6101573A Bit line and/or match line partitioned content addressable memory 失效
标题翻译：位线和/或匹配线分隔内容可寻址存储器
公开(公告)号：US6101573A
公开(公告)日：2000-08-08
申请号：US96523
申请日：1998-06-12
申请人： Peter Guy Middleton , John Stuart Kelly , Michael Thomas Kilpatrick , Mark Allen Silla
发明人： Peter Guy Middleton , John Stuart Kelly , Michael Thomas Kilpatrick , Mark Allen Silla
IPC分类号： G06F12/08 , G11C15/00 , G06F12/14 , G06F13/16
CPC分类号： G06F12/0893 , G11C15/00 , Y02B60/1225
摘要： A cache memory 18 is formed of a content addressable memory 20 and a cache RAM 22. The content addressable memory 20 is divided into two or more sections by an AND gate array 28 that serves to selectively either block or unblock the bit lines 26 that supply an input data word to the bit storage and comparison cells 34 of the content addressable memory 20. The generation of match signals for each section is also selectively blocked by preventing the match signal discharge to ground. The match signals from a blocked section are not passed to the RAM 22. The AND gate array 28 and match signal disable may be controlled by the least significant bit of the input data word, higher order bits of the input data word or may be controlled by a bit selected by program control from among the bits of the input data word. When a portion of the bit lines 26 are blocked by the AND gate array 28, then the capacitance of the bit lines 26 that need to be driven is reduced and the number of match lines discharged is halved thereby reducing power consumption.
摘要翻译：高速缓冲存储器18由内容可寻址存储器20和高速缓存RAM22形成。内容可寻址存储器20由与门阵列28分成两部分或更多部分，其用于选择性地阻塞或解锁提供的位线26 输入数据字到内容可寻址存储器20的位存储和比较单元34中。通过防止匹配信号放电到地，每个部分的匹配信号的产生也被选择性地阻止。来自阻塞部分的匹配信号不被传递到RAM 22.与门阵列28和匹配信号禁用可以由输入数据字的最低有效位，输入数据字的较高位或可被控制通过由输入数据字的位中的程序控制选择的位。当位线26的一部分被AND门阵列28阻挡时，需要驱动的位线26的电容减小，并且排出的匹配线的数量减半，从而降低功耗。

2. 发明授权

US06366978B1 Cache memory 有权
标题翻译：高速缓存存储器
公开(公告)号：US06366978B1
公开(公告)日：2002-04-02
申请号：US09434491
申请日：1999-11-05
申请人： Peter Guy Middleton , Michael Thomas Kilpatrick
发明人： Peter Guy Middleton , Michael Thomas Kilpatrick
IPC分类号： G06F1200
CPC分类号： G06F17/30982 , G06F12/0893 , G06F12/12 , G11C15/04
摘要： A cache memory system 22 is described in which a content addressable memory 24 and a cache RAM memory 28 are provided. Each content addressable storage row has an associated hit line 18 and an access enable line 12. An index decoder 46 is provided for controlling cache replacement and cache maintenance operations. The hit line 18 is used for passing both hit signals to the cache RAM 28 and select signals generated by the index decoder 46. A gate 36 operating under control of a multiplexer controller 44 controls this dual-use of the hit line 18 in dependence upon a selected mode of operation. In some embodiments a fast block transfer may be performed by loading data from a first address A into the cache memory 22. A match for the TAG value of the first address A could then be performed and the corresponding hit signal asserted and latched within a latch 43. Upon a subsequent cycle the latched hit signal can be passed to an access enable line 12 to permit a new TAG value corresponding to a second address B to be written to the content addressable memory 24. The cached data values from the first address A are now present within the cache memory system 22 associated with a TAG value of the second address B. The dirty bit may be set to ensure that writeback occurs when the data value is removed from the cache memory 22 thereby ensuring data integrity.
摘要翻译：描述了一种缓存存储器系统22，其中提供内容可寻址存储器24和高速缓存RAM存储器28。每个内容可寻址存储行具有相关联的命中线18和访问使能线12.提供索引解码器46用于控制高速缓存替换和高速缓存维护操作。命中线18用于将两个命中信号传送到高速缓存RAM28并选择索引解码器46产生的信号。在多路复用器控制器44的控制下操作的门36控制命中线18的这种双重用途，依赖于选定的操作模式。在一些实施例中，可以通过将数据从第一地址A加载到高速缓存存储器22中来执行快速块传输。然后可以执行对于第一地址A的TAG值的匹配，并且相应的命中信号被断言并锁存在锁存器在随后的周期中，锁存的命中信号可被传递到访问允许线12，以允许对应于第二地址B的新TAG值被写入内容可寻址存储器24.来自第一地址A的缓存的数据值现在存在于与第二地址B的TAG值相关联的高速缓冲存储器系统22内。可以设置脏位以确保当从高速缓冲存储器22移除数据值从而确保数据完整性时发生回写。

3. 发明授权

US6018794A Data processing apparatus and method for generating timing signals for a self-timed circuit 失效
标题翻译：用于产生自定时电路的定时信号的数据处理装置和方法
公开(公告)号：US6018794A
公开(公告)日：2000-01-25
申请号：US841594
申请日：1997-04-30
申请人： Michael Thomas Kilpatrick
发明人： Michael Thomas Kilpatrick
IPC分类号： G11C7/06 , G11C7/22 , G06F13/00 , G11C11/407 , G11C11/413
CPC分类号： G11C7/22 , G11C7/06
摘要： A self-timed data processing circuit and method of operation of such a circuit are disclosed. The circuit comprises a plurality of components, such as memory cells, arranged to generate substantially simultaneously a plurality of first output signals, each representing variable data bits. A timed circuit, which may include a plurality of sense amplifiers, is then arranged to receive the first output signals and to generate second output signals for use in subsequent data processing operations, the information content of the second output signals being dependent on the data bits represented by the first output signals. A subset of the components, such as memory cells storing dirty and valid bits for a cache memory, are arranged to generate first output signals representing data bits that are coded so as to cause at least one of the second output signals generated by the timed circuit to transition from its state prior to the generation of the first output signals. Control circuitry, responsive to the state transition of the at least one second output signal, is then used to generate a timing signal used to control the operation of the timed circuit to provide reduced power consumption. This also enables a reference timing signal to be created to self-time the data processing circuit, without the need to duplicate the critical path of the data processing circuit by using additional reference components.
摘要翻译：公开了一种自定时数据处理电路和这种电路的操作方法。电路包括诸如存储器单元的多个组件，其被布置为基本同时产生多个第一输出信号，每个第一输出信号表示可变数据位。然后，可以包括多个读出放大器的定时电路被布置成接收第一输出信号并产生用于后续数据处理操作的第二输出信号，第二输出信号的信息内容取决于数据位由第一个输出信号表示。组件的子集，例如存储用于高速缓冲存储器的脏和有效位的存储器单元被布置成产生表示数据位的第一输出信号，该数据位被编码，以便使定时电路产生的第二输出信号中的至少一个在产生第一输出信号之前从其状态转变。响应于至少一个第二输出信号的状态转换的控制电路然后用于产生用于控制定时电路的操作以提供降低的功耗的定时信号。这也使得能够创建参考定时信号以自动地对数据处理电路进行自动化，而不需要通过使用附加的参考组件来复制数据处理电路的关键路径。

4. 发明授权

US5875465A Cache control circuit having a pseudo random address generator 失效
标题翻译：高速缓存控制电路具有伪随机地址发生器
公开(公告)号：US5875465A
公开(公告)日：1999-02-23
申请号：US832091
申请日：1997-04-03
申请人： Michael Thomas Kilpatrick , Simon Charles Watt , Guy Larri
发明人： Michael Thomas Kilpatrick , Simon Charles Watt , Guy Larri
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/128 , G06F12/0848 , G06F12/126
摘要： A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache memory between instruction words and data words in dependence upon whether the central processing unit 4 indicates with signal I/D whether the word to be stored within the cache memory 2 resulted from an instruction word cache miss or data word cache miss. The cache memory array 2 may have a programmably sized portion locked down so that it is not replaced. The selection within the complementary programmable range where overwriting takes place uses a pseudo random selection technique using pseudo random number generator in the form of a linear feedback shift register triggering incrementing of a counter.
摘要翻译：一种包含高速缓冲存储器2和中央处理单元的数据处理系统。存储控制电路10响应于可编程分区设置PartVal，以根据中央处理单元4是否用信号I / D指示要存储在高速缓存存储器2中的单词来指示高速缓存在指令字和数据字之间由指令字缓存未命中或数据字高速缓存未命中引起。缓存存储器阵列2可以具有可编程尺寸的部分锁定，使得它不被替换。在进行重写的互补可编程范围内的选择使用伪随机数选择技术，该伪随机数生成器以线性反馈移位寄存器的形式触发递增计数器。

5. 发明授权

US06218879B1 S-R flip-flop circuit 有权
标题翻译： S-R触发器电路
公开(公告)号：US06218879B1
公开(公告)日：2001-04-17
申请号：US09266892
申请日：1999-03-12
申请人： Michael Thomas Kilpatrick
发明人： Michael Thomas Kilpatrick
IPC分类号： H03K3037
CPC分类号： H03K3/012 , H03K3/356113
摘要： An S-R flip-flop circuit is provided using two stacks of gates 2, 6 with an internal signal Int stored therebetween. Feedback from the output O is used to switch the state of the internal signal Int in a manner that provides an edge-triggered response for at least one of the inputs.
摘要翻译：使用两个门2,6的堆叠提供S-R触发器电路，其间存在内部信号Int。来自输出O的反馈用于以对至少一个输入提供边沿触发响应的方式切换内部信号Int的状态。

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