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1. 发明授权

US06552949B1 Reducing leakage current in a memory device 有权
标题翻译：降低存储器件中的漏电流
公开(公告)号：US06552949B1
公开(公告)日：2003-04-22
申请号：US10062567
申请日：2002-02-05
申请人： Mark Allen Silla , Arthur R Piejko , Michael Louis Brauer , Gerard Richard Williams, III
发明人： Mark Allen Silla , Arthur R Piejko , Michael Louis Brauer , Gerard Richard Williams, III
IPC分类号： G11C700
CPC分类号： G11C11/417 , G11C7/1048 , G11C7/12 , G11C7/20 , G11C11/419 , G11C2207/2227
摘要： The present invention relates to a memory device and method for reducing leakage current during a power down mode of operation. The memory device comprises a column of memory cells, with each memory cell being arranged to store a data value, and a pair of bit lines coupled to the column of memory cells. Bit line precharge circuitry is provided for precharging the pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in the column is selected in an evaluate phase following the precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell. In accordance with the present invention, the memory device further comprises power down control circuitry arranged when the memory device is to enter a power down mode to prevent the bit line precharge circuitry from precharging the pair of bit lines, and selector circuitry arranged when the memory device is to enter the power down mode to ensure that none of the memory cells in the column are selected. It has been found that by taking this approach during the power down mode of operation, a significant reduction in the leakage current is observed.
摘要翻译：本发明涉及一种用于在掉电操作模式期间减少泄漏电流的存储器件和方法。存储器件包括一列存储器单元，每个存储器单元被布置成存储数据值，以及耦合到存储器单元列的一对位线。位线预充电电路被提供用于在预充电阶段期间将一对位线预充电到预定电压电平，该位位线布置成使得当在预充电之后的评估阶段选择列中的特定存储单元时一对位线之间的电压电平的相对变化指示存储在所选存储单元内的数据值。根据本发明，存储器件还包括掉电控制电路，当存储器件要进入掉电模式时被布置，以防止位线预充电电路对该对位线进行预充电;以及选择器电路，当存储器设备进入掉电模式，以确保列中没有一个存储单元被选中。已经发现，通过在断电操作模式期间采取该方法，可以观察到泄漏电流的显着降低。

2. 发明授权

US6101573A Bit line and/or match line partitioned content addressable memory 失效
标题翻译：位线和/或匹配线分隔内容可寻址存储器
公开(公告)号：US6101573A
公开(公告)日：2000-08-08
申请号：US96523
申请日：1998-06-12
申请人： Peter Guy Middleton , John Stuart Kelly , Michael Thomas Kilpatrick , Mark Allen Silla
发明人： Peter Guy Middleton , John Stuart Kelly , Michael Thomas Kilpatrick , Mark Allen Silla
IPC分类号： G06F12/08 , G11C15/00 , G06F12/14 , G06F13/16
CPC分类号： G06F12/0893 , G11C15/00 , Y02B60/1225
摘要： A cache memory 18 is formed of a content addressable memory 20 and a cache RAM 22. The content addressable memory 20 is divided into two or more sections by an AND gate array 28 that serves to selectively either block or unblock the bit lines 26 that supply an input data word to the bit storage and comparison cells 34 of the content addressable memory 20. The generation of match signals for each section is also selectively blocked by preventing the match signal discharge to ground. The match signals from a blocked section are not passed to the RAM 22. The AND gate array 28 and match signal disable may be controlled by the least significant bit of the input data word, higher order bits of the input data word or may be controlled by a bit selected by program control from among the bits of the input data word. When a portion of the bit lines 26 are blocked by the AND gate array 28, then the capacitance of the bit lines 26 that need to be driven is reduced and the number of match lines discharged is halved thereby reducing power consumption.
摘要翻译：高速缓冲存储器18由内容可寻址存储器20和高速缓存RAM22形成。内容可寻址存储器20由与门阵列28分成两部分或更多部分，其用于选择性地阻塞或解锁提供的位线26 输入数据字到内容可寻址存储器20的位存储和比较单元34中。通过防止匹配信号放电到地，每个部分的匹配信号的产生也被选择性地阻止。来自阻塞部分的匹配信号不被传递到RAM 22.与门阵列28和匹配信号禁用可以由输入数据字的最低有效位，输入数据字的较高位或可被控制通过由输入数据字的位中的程序控制选择的位。当位线26的一部分被AND门阵列28阻挡时，需要驱动的位线26的电容减小，并且排出的匹配线的数量减半，从而降低功耗。

3. 发明授权

US07053675B2 Switching between clocks in data processing 失效
标题翻译：在数据处理中切换时钟
公开(公告)号：US07053675B2
公开(公告)日：2006-05-30
申请号：US10626871
申请日：2003-07-25
申请人： Richard Slobodnik , Gerard Richard Williams , Mark Allen Silla
发明人： Richard Slobodnik , Gerard Richard Williams , Mark Allen Silla
IPC分类号： G06F1/04
CPC分类号： G06F1/08
摘要： A processor clock control device is disclosed that is operable to control switching between clock signals input to a processor in a glitch-free way. The processor clock control device comprises: at least two clock signal inputs each operable to receive a clock signal, said clock signals comprising a first and a second clock signal; a sensor operable to sense said first and said second clock signals; a clock signal output operable to output a clock signal for input to a processor; and a clock switching signal input for receiving a switching signal operable to control switching of said clock signal output from said first clock signal to said second clock signal; wherein said processor clock control device is operable on receipt of said clock switching signal to sense said first clock signal and when said first clock signal transitions from a first predetermined level to a second level, said processor clock control device is operable to hold said clock signal output at said second level, and then to sense said second clock signal and when said second clock signal transitions from said second level to said first predetermined level to output said second clock signal.
摘要翻译：公开了一种处理器时钟控制装置，其可操作以控制以无毛刺方式输入到处理器的时钟信号之间的切换。处理器时钟控制装置包括：至少两个时钟信号输入，每个可操作以接收时钟信号，所述时钟信号包括第一和第二时钟信号; 传感器，其可操作以感测所述第一和所述第二时钟信号; 时钟信号输出，其可操作以输出用于输入到处理器的时钟信号; 以及时钟切换信号输入，用于接收可操作以控制从所述第一时钟信号输出到所述第二时钟信号的所述时钟信号的切换的切换信号; 其中所述处理器时钟控制装置在接收到所述时钟切换信号以操作所述第一时钟信号时可操作，并且当所述第一时钟信号从第一预定电平转变到第二电平时，所述处理器时钟控制装置可操作以保持所述时钟信号在所述第二电平输出，然后感测所述第二时钟信号，并且当所述第二时钟信号从所述第二电平转换到所述第一预定电平时，输出所述第二时钟信号。

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