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    • 9. 发明授权
    • Electronic postage meter having memory write access second chance hard
timer means
    • 具有存储器写入访问的电子邮资计算机二次机会硬定时器装置
    • US5438519A
    • 1995-08-01
    • US989673
    • 1993-02-10
    • Peter C. DiGiulio
    • Peter C. DiGiulio
    • G06F11/00G06F11/14G07B17/00G11C29/00G06F17/60
    • G06F11/0757G06F11/141G07B17/00362G07B2017/00258G07B2017/00338G07B2017/00395G07B2017/0079G11C29/74
    • A postage meter control system includes a microcomputer having a programmable microprocessor. The microcomputer is in communication with a decoder integrated circuit (Decoder IC). The Decoder IC has a first write control flip-flop and a second write control flip-flop, as in the preferred embodiment there are redundant non-volatile memories. Each control flip-flop has an output to a respective AND gate. The Decoder IC includes a dual timer which has an output to the control flip-flops. As a result, when the microcomputer enters write routine, the timer releases the control flip-flops to allow the system to be write enabled. If the write routine encounters a error, resulting in the timer timing out, the timer resets the control flip-flop and communicates with the microcomputer to try a retry. A more detailed description, and other features and advantages will become apparent in conjunction with the detailed description of the preferred embodiment.
    • 邮资计费器控制系统包括具有可编程微处理器的微型计算机。 微型计算机与解码器集成电路(解码器IC)通信。 解码器IC具有第一写入控制触发器和第二写入控制触发器,如在优选实施例中,存在冗余的非易失性存储器。 每个控制触发器具有到相应的与门的输出。 解码器IC包括具有到控制触发器的输出的双重定时器。 结果,当微计算机进入写入例程时,定时器释放控制触发器以允许系统被写入使能。 如果写入例程遇到错误,导致定时器超时,定时器复位控制触发器并与微型计算机通信以尝试重试。 结合优选实施例的详细描述,更详细的描述和其它特征和优点将变得显而易见。
    • 10. 发明授权
    • Electronic postage meter having a memory map decoder
    • 具有存储器映射解码器的电子邮资计费器
    • US4901273A
    • 1990-02-13
    • US710800
    • 1985-03-12
    • Peter C. DiGiulio
    • Peter C. DiGiulio
    • G07B17/00
    • G07B17/00362G07B2017/00258G07B2017/00403
    • An electronic postage meter has an improved memory selection circuit wherein custom memory map decoder circuit with resolution down to a single byte location is used to provide selection enabling signals to insure the selection of an appropriate device only when the addresses appropriate to that device are communicated. In accordance with the invention, at least two nonvolatile memories are provided. Writing to either of these nonvolatile memories is inhibited unless one and only one memory is selected. The circuit also prevents the selection of either of the nonvolatile memories in the event that the write strobe signal to the memories is held active.
    • 电子邮资计量表具有改进的存储器选择电路,其中具有分辨率低至单个字节位置的自定义存储器映射解码器电路被用于提供选择使能信号,以便仅当适合于该设备的地址被通信时确保适当的设备的选择。 根据本发明,提供至少两个非易失性存储器。 除非选择一个和仅一个存储器,否则写入这些非易失性存储器中的任何一个被禁止。 在存储器的写入选通信号保持活动的情况下,电路还防止选择任一个非易失性存储器。