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1. 发明授权

US06235544B1 Seed metal delete process for thin film repair solutions using direct UV laser 失效
标题翻译：种子金属删除工艺用于使用直接UV激光的薄膜修复解决方案
公开(公告)号：US06235544B1
公开(公告)日：2001-05-22
申请号：US09295131
申请日：1999-04-20
申请人： Peter A. Franklin , Charles J. Hendricks , Richard P. Surprenant , Stephen J. Tirch, III , Thomas A. Wassick , James P. Wood
发明人： Peter A. Franklin , Charles J. Hendricks , Richard P. Surprenant , Stephen J. Tirch, III , Thomas A. Wassick , James P. Wood
IPC分类号： G01R3126
CPC分类号： H01L21/485
摘要： A multilayer thin film structure (MLTF) is provided having no extraneous via-pad connection strap plated metallurgy for defective vias needing removal. The method for making or repairing the MLTF comprises determining interconnection defects in the MLTF at a thin film layer adjacent to the top metal layer of the structure, applying a top surface dielectric layer and forming vias in the layer, applying a metal conducting layer and removing the metal conducting layer for via-pad connection straps of defective vias and at the intersection of XY lines used in the repair, defining the top surface metallization including a series of orthogonal X conductor repair lines and Y conductor repair lines using a photoresist and lithography and then using a phototool to selectively expose the photoresist to define top surface strap connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization using additive or subtractive metallization techniques.
摘要翻译：提供了一种多层薄膜结构（MLTF），其中没有外部通孔焊盘连接带电镀冶金用于需要去除的缺陷通孔。用于制造或修复MLTF的方法包括：在与该结构的顶部金属层相邻的薄膜层处确定MLTF中的互连缺陷，施加顶表面介电层并在该层中形成通孔，施加金属导电层并除去用于通孔焊盘连接带的金属导电层和用于修复的XY线的相交处，限定包括一系列正交X导体修复线的顶表面金属化和使用光致抗蚀剂和光刻的Y导体修复线，然后使用光学工具选择性地暴露光致抗蚀剂以限定修复互连和/或制造EC所需的顶表面带连接，以及使用添加或减色金属化技术形成顶表面金属化。

2. 发明授权

US06753688B2 Interconnect package cluster probe short removal apparatus and method 失效
标题翻译：互连封装集群探头短路去除装置和方法
公开(公告)号：US06753688B2
公开(公告)日：2004-06-22
申请号：US09829749
申请日：2001-04-10
申请人： Roger M. Eddy , Charles J. Hendricks , Thomas Morrison , Robert N. Wiggin , Brian J. Wojszynski
发明人： Roger M. Eddy , Charles J. Hendricks , Thomas Morrison , Robert N. Wiggin , Brian J. Wojszynski
IPC分类号： G01R3102
CPC分类号： H05K3/225 , G01R31/2805
摘要： A method and structure for an electronic circuit test and repair apparatus includes both of at least one wiring analyzer to locate circuit shorts and a current source to provide current sufficient to attempt to remove any identified shorts.
摘要翻译：用于电子电路测试和修复设备的方法和结构包括用于定位电路短路的至少一个布线分析仪和电流源，以提供足以尝试去除任何识别的短路的电流。

3. 发明授权

US6054863A System for testing circuit board integrity 失效
标题翻译：电路板完整性测试系统
公开(公告)号：US6054863A
公开(公告)日：2000-04-25
申请号：US710130
申请日：1996-09-11
申请人： Thomas Morrison , Siegfried Geyer , Charles J. Hendricks , Klaus Probst
发明人： Thomas Morrison , Siegfried Geyer , Charles J. Hendricks , Klaus Probst
IPC分类号： G01R31/28 , G01R31/02 , H01H31/02
CPC分类号： G01R31/2803
摘要： A system for testing circuit boards comprising a probe network having a plurality of probes wherein each probe is adapted for contacting an end of a corresponding circuit board network and wherein each probe and network define a node having an address. The system further comprises a control device that includes a node address generator and a timing circuit having an output for outputting a pulse to the node having the address generated by the node address generator and for coupling the remaining nodes to electrical ground. The system further comprises a comparator for comparing the pulse outputted by the timing circuit to predetermined data.
摘要翻译：一种用于测试电路板的系统，包括具有多个探针的探针网络，其中每个探针适于接触相应电路板网络的端部，并且其中每个探针和网络限定具有地址的节点。该系统还包括控制装置，其包括节点地址发生器和定时电路，该定时电路具有用于向具有由节点地址发生器产生的地址的节点输出脉冲并用于将剩余节点耦合到电接地的输出。该系统还包括比较器，用于将定时电路输出的脉冲与预定数据进行比较。

4. 发明授权

US07808257B2 Ionization test for electrical verification 失效
标题翻译：电验证电离试验
公开(公告)号：US07808257B2
公开(公告)日：2010-10-05
申请号：US10595541
申请日：2003-11-12
申请人： Christopher W. Cline , Edward J. Yarmchuk , Vincent A. Arena , Donald A. Merte , Thomas Picunko , Brian J. Wojszynski , Charles J. Hendricks , Michael E. Scaman , Robert S. Olyha, Jr. , Arnold Halperin
发明人： Christopher W. Cline , Edward J. Yarmchuk , Vincent A. Arena , Donald A. Merte , Thomas Picunko , Brian J. Wojszynski , Charles J. Hendricks , Michael E. Scaman , Robert S. Olyha, Jr. , Arnold Halperin
IPC分类号： G01R31/302
CPC分类号： G01R31/2805 , G01R19/0061 , G01R31/302
摘要： A method and apparatus for the non-contact electrical test of both opens and shorts in electronic substrates. Top surface electrical test features are exposed to an ionization source under ambient conditions and the subsequent charge build up is measured as a drain current by probes contacting corresponding bottom surface features. Opens are detected by an absence of a drain current and shorts are detected by turning off the ionization source and re-measuring the bottom surface probes with a varying bias applied to each probe in the array.
摘要翻译：用于电子基板中的开口和短路的非接触电测试的方法和装置。顶部表面电测试特征在环境条件下暴露于电离源，随后的电荷积聚通过探针接触相应的底表面特征作为漏极电流测量。通过不存在漏极电流来检测开路，并且通过关闭电离源并且利用施加到阵列中的每个探针的变化偏置来重新测量底表面探针来检测短路。

5. 发明授权

US4534816A Single wafer plasma etch reactor 失效
标题翻译：单晶片等离子体蚀刻反应器
公开(公告)号：US4534816A
公开(公告)日：1985-08-13
申请号：US623670
申请日：1984-06-22
申请人： Lee Chen , Charles J. Hendricks , Gangadhara S. Mathad , Stanley J. Poloncic
发明人： Lee Chen , Charles J. Hendricks , Gangadhara S. Mathad , Stanley J. Poloncic
IPC分类号： H01L21/302 , H01J37/32 , H01L21/00 , H01L21/3065 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/02
CPC分类号： H01L21/67069 , H01J37/3244 , H01J37/32532 , H01J37/32623
摘要： A high pressure, high etch rate single wafer plasma reactor having a fluid cooled upper electrode including a plurality of small diameter holes or passages therethrough to provide uniform reactive gas distribution over the surface of a wafer to be etched. A fluid cooled lower electrode is spaced from the upper electrode to provide an aspect ratio (wafer diameter: spacing) greater than about 25, and includes an insulating ring at its upper surface. The insulating ring protrudes above the exposed surface of the lower electrode to control the electrode spacing and to provide a plasma confinement region whereby substantially all of the RF power is dissipated by the wafer. A plurality of spaced apart, radially extending passages through the insulating ring provide a means of uniformly exhausting the reactive gas from the plasma confinement region. Affixed to the upper electrode is a first housing which supplies reactive gas and cooling fluid, and a baffle affixed to the first housing intermediate the upper electrode and a gas inlet forms a plenum above the upper electrode and ensures uniform reactive gas distribution thereover. The first housing and upper electrode are contained within a second housing with an insulating housing therebetween. The upper and lower electrodes are electrically isolated from each other and from ground, so that either or both electrodes may be powered.
摘要翻译：高压，高蚀刻速率的单晶片等离子体反应器，其具有流体冷却的上部电极，其包括多个小直径孔或穿过其中的通道，以在要蚀刻的晶片的表面上提供均匀的反应气体分布。流体冷却的下电极与上电极隔开以提供大于约25的纵横比（晶片直径：间距），并且在其上表面包括绝缘环。绝缘环突出在下电极的暴露表面之上，以控制电极间距并提供等离子体约束区域，从而基本上所有的RF功率都被晶片消散。通过绝缘环的多个间隔开的径向延伸通道提供均匀排出来自等离子体限制区域的反应气体的装置。与上电极相连的是提供反应性气体和冷却流体的第一壳体，以及固定在上电极之间的第一壳体的挡板和气体入口在上电极上形成集气室，并确保其上的均匀的反应气体分布。第一壳体和上电极容纳在第二壳体中，其间具有绝缘壳体。上电极和下电极彼此电隔离并且与地电隔离，使得电极或电极都可以被供电。

6. 发明授权

US4340461A Modified RIE chamber for uniform silicon etching 失效
标题翻译：改进的RIE室，用于均匀的硅蚀刻
公开(公告)号：US4340461A
公开(公告)日：1982-07-20
申请号：US185831
申请日：1980-09-10
申请人： Charles J. Hendricks , William W. Hicks , John H. Keller
发明人： Charles J. Hendricks , William W. Hicks , John H. Keller
IPC分类号： H01L21/302 , H01J37/32 , H01L21/3065 , C23C15/00 , C23F1/00
CPC分类号： H01J37/32623 , H01J37/32633
摘要： A plasma enhancing baffle plate is employed in conjunction with the anode of an RIE system to provide uniform silicon etching. The baffle plate is conductively coupled to and provided in relatively close proximity to the anode to form a constricted chamber region between anode and baffle plate. With the constricted chamber open to the RIE chamber through aperture means in the baffle plate the total surface area of the anode is increased, such that when the system is biased to operate in an RIE mode an increase in the generation of neutral etching species is effected. Various aperture arrangements may be employed to provide different patterns of neutral etching species generation, in accordance with the peculiar characteristics of the system employed.
摘要翻译：等离子体增强挡板与RIE系统的阳极结合使用以提供均匀的硅蚀刻。挡板与阳极电导耦合并相对靠近地设置，以在阳极和挡板之间形成收缩室区域。在收缩室通过挡板中的孔装置向RIE腔室开放的情况下，阳极的总表面积增加，使得当系统被偏置以在RIE模式下工作时，实现中性蚀刻物质的产生的增加。根据所使用的系统的特有特征，可以采用各种孔径布置来提供生成不同中性蚀刻物质的图案。

7. 发明授权

US06984997B2 Method and system for testing multi-chip integrated circuit modules 失效
标题翻译：用于测试多芯片集成电路模块的方法和系统
公开(公告)号：US06984997B2
公开(公告)日：2006-01-10
申请号：US10714215
申请日：2003-11-13
申请人： Yuet-Ying Yu , Paul F. Bodenweber , Charles J. Hendricks , Frank C. Seelmann
发明人： Yuet-Ying Yu , Paul F. Bodenweber , Charles J. Hendricks , Frank C. Seelmann
IPC分类号： G01R31/02
CPC分类号： G01R31/2886
摘要： A system and method for utilizing a multi-probe tester to test an electrical device having a plurality of contact pads. Multi-probe tester test probes and electrical device contact pads are arrayed in a common distribution pitch, wherein at least one test probe is masked, thereby preventing the at least one test probe from returning a test result to the testing apparatus. In one embodiment mask membrane physically prevents at least one test probe from making contact with the electrical device. In another embodiment at least one software command is provided configured to cause an input from at least one test probe to be disregarded during a test routine. Another embodiment features both mask membrane and software command probe masking.
摘要翻译：一种利用多探针测试仪测试具有多个接触垫的电气设备的系统和方法。多探针测试器测试探针和电气设备接触垫以公共分布间距排列，其中至少一个测试探针被掩蔽，从而防止至少一个测试探针将测试结果返回到测试设备。在一个实施例中，掩膜膜物理地防止至少一个测试探针与电气装置接触。在另一个实施例中，提供至少一个软件命令被配置为在测试例程期间使来自至少一个测试探针的输入被忽略。另一个实施例具有掩膜膜和软件命令探针掩蔽。

8. 发明授权

US06281692B1 Interposer for maintaining temporary contact between a substrate and a test bed 失效
标题翻译：用于保持基板和试验台之间的临时接触的插入件
公开(公告)号：US06281692B1
公开(公告)日：2001-08-28
申请号：US09166468
申请日：1998-10-05
申请人： Paul F. Bodenweber , Ralph R. Comulada , Mukta S. Farooq , Charles J. Hendricks , Philo B. Hodge , Vincent P. Peterson , Terence W. Spoor , Kathleen M. Wiley , Yuet-Ying Yu
发明人： Paul F. Bodenweber , Ralph R. Comulada , Mukta S. Farooq , Charles J. Hendricks , Philo B. Hodge , Vincent P. Peterson , Terence W. Spoor , Kathleen M. Wiley , Yuet-Ying Yu
IPC分类号： G01R3102
CPC分类号： G01R1/07378
摘要： Disclosed is an interposer and test structure for making contact between a substrate and a test bed. One embodiment of the interposer has a floating, rigid conductive element in a nonconductive body which makes temporary contact between the test bed and the substrate. In another embodiment of the invention, the interposer includes two layers of material, in which one layer includes pogo pins for contacting the substrate and the other layer includes pads for contacting the test bed. The pogo pins are on a grid spacing corresponding to that of the substrate input/output pads while the interposer pads are on a grid spacing corresponding to that of the pogo pin contactors of the test bed.
摘要翻译：公开了一种用于在基板和试验台之间进行接触的插入件和测试结构。插入器的一个实施例在非导体中具有浮动的刚性导电元件，其使得测试台与基板之间暂时接触。在本发明的另一个实施例中，插入件包括两层材料，其中一层包括用于接触衬底的弹簧针，另一层包括用于接触测试台的衬垫。弹簧针位于与衬底输入/输出焊盘相对应的栅格间隔上，而插入垫位于对应于测试台的弹簧针接触器的栅格间隔上。

9. 发明授权

US4600464A Plasma etching reactor with reduced plasma potential 失效
标题翻译：具有降低等离子体电位的等离子体蚀刻反应器
公开(公告)号：US4600464A
公开(公告)日：1986-07-15
申请号：US729445
申请日：1985-05-01
申请人： Brian H. Desilets , Thomas A. Gunther , Charles J. Hendricks , John H. Keller
发明人： Brian H. Desilets , Thomas A. Gunther , Charles J. Hendricks , John H. Keller
IPC分类号： H01L21/302 , C23F4/00 , H01J37/32 , H01L21/3065 , B44C1/22 , C03C15/00 , C03C25/06 , C23F1/02
CPC分类号： H01J37/32623 , H01J37/32633
摘要： An improved plasma reactor for uniformly etching a large number of semiconductor wafers at a reduced plasma potential includes, in one embodiment, a grounded plate mounted intermediate the cathode and the top plate of a reactor chamber, the top plate and the chamber walls forming the reactor anode. The grounded plate is spaced apart from the chamber top plate a distance sufficient to allow a plasma to be established between the grounded plate and the top plate, and the distance between the grounded plate and the cathode is large enough not to disturb the field in the proximity of the wafers being etched. The plate can be apertured to facilitate etchant gas flow. According to another embodiment of the invention at least two grounded plates are employed, spaced apart from each other and from the upper surface of the reactor plasma chamber.
摘要翻译：在一个实施例中，用于在等离子体电位降低的情况下均匀地蚀刻大量半导体晶片的改进的等离子体反应器包括安装在反应器室的阴极和顶板之间的接地板，顶板和形成反应器的室壁阳极。接地板与腔室顶板隔开足够的距离，以允许在接地板和顶板之间建立等离子体，并且接地板和阴极之间的距离足够大，不会扰乱被蚀刻的晶片的接近度。板可以是开孔的，以便于蚀刻剂气体流动。根据本发明的另一个实施例，使用至少两个接地板，彼此间隔开并且与反应器等离子体室的上表面间隔开。

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