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1. 发明申请

US20080141203A1 ITERATIVE METHOD FOR REFINING INTEGRATED CIRCUIT LAYOUT USING COMPASS OPTICAL PROXIMITY CORRECTION (OPC) 有权
标题翻译：使用对比度校正（OPC）进行整合电路布局的迭代方法
公开(公告)号：US20080141203A1
公开(公告)日：2008-06-12
申请号：US12033102
申请日：2008-02-19
申请人： Michael E. Scaman
发明人： Michael E. Scaman
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping edge fragments according to directional orientations, selecting an edge fragment or a combination of non-opposing edge fragments, calculating an edge placement error of the selected edge fragment and proximally shifting the edge fragment until a quality limitation is met.
摘要翻译：本发明是一种迭代方法或程序，涉及一系列光学邻近校正（OPC）处理步骤，用于在光刻工艺期间精炼晶片上的集成电路设计布局。迭代方法可以应用为系统和计算机程序，以根据方向取向，选择边缘片段或非相对边缘片段的组合来分类和分组边缘片段，计算所选边缘片段的边缘放置误差和近端移动边缘片段直到满足质量限制。

2. 发明授权

US07187179B1 Wiring test structures for determining open and short circuits in semiconductor devices 失效
标题翻译：用于确定半导体器件的开路和短路的接线测试结构
公开(公告)号：US07187179B1
公开(公告)日：2007-03-06
申请号：US11163450
申请日：2005-10-19
申请人： Michael E. Scaman , Toshiaki Yanagisawa
发明人： Michael E. Scaman , Toshiaki Yanagisawa
IPC分类号： G01R31/08
CPC分类号： G01R31/2884 , G01R31/2853 , H01L2924/0002 , H01L2924/00
摘要： A wiring test structure includes a plurality of wiring traces configured in an interleaving spiral pattern. At least one of the plurality of wiring traces configured for open circuit testing therein, and at least a pair of the plurality of wiring traces is configured for short circuit testing therebetween.
摘要翻译：布线测试结构包括以交错螺旋图案配置的多个布线迹线。配置用于其中进行开路测试的多个布线轨迹中的至少一个，并且至少一对多个布线轨迹被配置用于其间的短路测试。

3. 发明授权

US6141093A Method and apparatus for locating power plane shorts using polarized light microscopy 失效
标题翻译：使用偏光显微镜定位电源平面短路的方法和装置
公开(公告)号：US6141093A
公开(公告)日：2000-10-31
申请号：US139515
申请日：1998-08-25
申请人： Bernell E. Argyle , Arnold Halperin , Michael E. Scaman , Edward J. Yarmchuk
发明人： Bernell E. Argyle , Arnold Halperin , Michael E. Scaman , Edward J. Yarmchuk
IPC分类号： G01N21/21 , G01R31/311 , G01N21/00 , G01R27/14
CPC分类号： G01N21/21 , G01R31/311
摘要： An apparatus and corresponding method for detecting, locating, or defining a short in a thin-film module. The apparatus includes a mechanical fixture supporting the module. A current source provides a current pulse to the module which produces a magnetic field and heating nearby the short which turns on and off as the pulsed current in the short turns on and off. Polarized light is directed onto the module, with an intermediate element disposed between the module and the source of the polarized light. The intermediate element may be a stress birefringent coating (e.g., a polyimide insulating layer) disposed on the module and onto which the polarized light is directed. The sample is rotated 0 to 45 degrees to maximize the birefringent effect. Alternatively, the intermediate element may be a magneto-optical Faraday rotator. A microscope is used to observe the module, facilitating identification of a short by the twisting of the polarization of the light as the short expands and shrinks in response to the heating or in response to the localized magnetic field. The preferred rotator is a composite having a garnet substrate, an iron garnet film disposed on the substrate, and a thin aluminum mirror layer disposed on the iron garnet film. The apparatus and method of the present invention have several applications.
摘要翻译：一种用于检测，定位或限定薄膜模块中的短路的装置和相应方法。该装置包括支撑模块的机械夹具。电流源向模块提供电流脉冲，其产生磁场并在短路附近加热，其短路中的脉冲电流接通和断开时导通和截止。偏振光被引导到模块上，中间元件设置在模块和偏振光源之间。中间元件可以是设置在模块上并且偏振光被引导到其上的应力双折射涂层（例如，聚酰亚胺绝缘层）。样品旋转0至45度以最大化双折射效应。或者，中间元件可以是磁光法拉第旋转器。使用显微镜来观察模块，通过随着短路的扩展和响应于加热或响应于局部磁场而收缩，通过扭转光的偏振来促进短路的识别。优选的旋转体是具有石榴石基材，设置在基材上的铁石榴石薄膜和设置在铁石榴石薄膜上的薄铝镜面层的复合体。本发明的装置和方法有几个应用。

4. 发明授权

US5821759A Method and apparatus for detecting shorts in a multi-layer electronic package 失效
标题翻译：用于检测多层电子封装中的短路的方法和装置
公开(公告)号：US5821759A
公开(公告)日：1998-10-13
申请号：US807076
申请日：1997-02-27
申请人： Michael E. Scaman , Edward J. Yarmchuk , Yuet-Ying Yu
发明人： Michael E. Scaman , Edward J. Yarmchuk , Yuet-Ying Yu
IPC分类号： G01R1/073 , G01R31/02 , G01R31/28
CPC分类号： G01R31/281 , G01R1/07314 , G01R31/025
摘要： A method and apparatus for locating shorts in multi-layer electronic packages during manufacture allows repair of the shorts and improved yields of the packages. A multi-layer package is fitted in a fixture after forming a thin film layer of metalization, and test is performed to detect shorts in the package. If a short is detected, a low current, high frequency signal is injected in pins on a bottom surface of the package. An approximate two dimensional location of the short is sensed by detecting an electromagnetic force induced by a magnetic field inductively coupled to a sensor proximate to the short on a top surface of the multi-layer package. The approximate location of the short is then inspected to precisely locate the short.
摘要翻译：在制造期间用于定位多层电子封装中的短路的方法和装置允许修复短路并提高封装的产量。在形成金属化薄膜层之后，在夹具中装配多层封装，并进行测试以检测封装中的短路。如果检测到短路，则将低电流，高频信号注入到封装底表面的引脚中。通过检测由感应耦合到靠近多层封装的顶表面上的短路的传感器的磁场感应的电磁力来感测短路的近似二维位置。然后检查短路的大致位置以精确定位短路。

5. 发明授权

US5818239A Simplified contactless test of MCM thin film I/O nets using a plasma 失效
标题翻译：使用等离子体的MCM薄膜I / O网络的简化非接触测试
公开(公告)号：US5818239A
公开(公告)日：1998-10-06
申请号：US811988
申请日：1997-03-05
申请人： Michael E. Scaman
发明人： Michael E. Scaman
IPC分类号： G01R31/02 , G01R31/304
CPC分类号： G01R31/2812 , G01R31/024 , G01R31/304
摘要： A gas panel plasma plate is used to detect shorts and opens on a thin film surface of a multilayer ceramic module (MCM) through biasing a circuit of the module through bottom surface module (BSM) pins to produce a glow within the plasma plate. A grounded plane is placed above the module to be tested, and the gap between the module and the plane is filled with a gas. A plasma discharge is created by biasing the circuit. The current produced at the BSM pin by the plasma discharge is monitored. The monitored current of the circuit under test is compared to a current range of a known good module. In the alternative, the light flux produced by the plasma discharge is monitored, and the monitored light flux is compared to a light flux range of a known good module.
摘要翻译：气体板等离子体板用于通过使模块的电路通过底表面模块（BSM）引脚偏置来在等离子体板中产生辉光，来检测多层陶瓷模块（MCM）的薄膜表面上的短路和开路。将接地平面放置在要测试的模块上方，并且模块和平面之间的间隙充满气体。通过偏置电路产生等离子体放电。监测通过等离子体放电在BSM引脚产生的电流。将被测电路的监测电流与已知的良好模块的电流范围进行比较。在替代方案中，监测由等离子体放电产生的光通量，并将所监视的光通量与已知的良好模块的光通量范围进行比较。

6. 发明授权

US07685544B2 Testing pattern sensitive algorithms for semiconductor design 有权
标题翻译：用于半导体设计的测试模式敏感算法
公开(公告)号：US07685544B2
公开(公告)日：2010-03-23
申请号：US11947254
申请日：2007-11-29
申请人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
发明人： David L. DeMaris , Timothy G. Dunham , William C. Leipold , Daniel N. Maynard , Michael E. Scaman , Shi Zhong
IPC分类号： G06F17/50
CPC分类号： G03F1/44 , G03F1/36
摘要： A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
摘要翻译：一种用于生成模式敏感算法的测试模式的计算机程序产品。程序产品包括从布局设计中提取特征样本的代码; 将特征样本分组成簇; 从布局设计中选择至少一个覆盖每个聚类的特征样本的区域; 并且将至少一个区域覆盖的每个模式布局保存为测试模式。

7. 发明授权

US07673279B2 Iterative method for refining integrated circuit layout using compass optical proximity correction (OPC) 有权
标题翻译：使用罗盘光学邻近校正（OPC）精化集成电路布局的迭代方法
公开(公告)号：US07673279B2
公开(公告)日：2010-03-02
申请号：US12033102
申请日：2008-02-19
申请人： Michael E. Scaman
发明人： Michael E. Scaman
IPC分类号： G06F17/50 , G06K9/00
CPC分类号： G03F1/36
摘要： The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping edge fragments according to directional orientations, selecting an edge fragment or a combination of non-opposing edge fragments, calculating an edge placement error of the selected edge fragment and proximally shifting the edge fragment until a quality limitation is met.
摘要翻译：本发明是一种迭代方法或程序，涉及一系列光学邻近校正（OPC）处理步骤，用于在光刻工艺期间精炼晶片上的集成电路设计布局。迭代方法可以应用为系统和计算机程序，以根据方向取向，选择边缘片段或非相对边缘片段的组合来分类和分组边缘片段，计算所选边缘片段的边缘放置误差和近端移动边缘片段直到满足质量限制。

8. 发明申请

US20100042967A1 MEEF REDUCTION BY ELONGATION OF SQUARE SHAPES 有权
标题翻译：通过平面形状的缩小来减少MEEF
公开(公告)号：US20100042967A1
公开(公告)日：2010-02-18
申请号：US12191493
申请日：2008-08-14
申请人： Derren N. Dunn , Michael M. Crouse , Henning Haffner , Michael E. Scaman
发明人： Derren N. Dunn , Michael M. Crouse , Henning Haffner , Michael E. Scaman
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method that purposely relaxes OPC algorithm constraints to allow post OPC mask shapes to elongate along one direction (particularly lowering the 1-dimensional MEEF in this direction with the result of an effectively overall lowered MEEF) to produce a pattern on wafer that is circular to within an acceptable tolerance.
摘要翻译：一种意图放松OPC算法约束以允许OPC掩模形状沿着一个方向伸长的方法（特别是在该方向上降低1维MEEF，结果是有效地降低了MEEF），从而在晶圆上产生一个圆形到在可接受的容限内。

9. 发明申请

US20070277145A1 ITERATIVE METHOD FOR REFINING INTEGRATED CIRCUIT LAYOUT USING COMPASS OPTICAL PROXIMITY CORRECTION (OPC) 有权
标题翻译：使用对比度校正（OPC）进行整合电路布局的迭代方法
公开(公告)号：US20070277145A1
公开(公告)日：2007-11-29
申请号：US11420534
申请日：2006-05-26
申请人： Michael E. Scaman
发明人： Michael E. Scaman
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping edge fragments according to directional orientations, selecting an edge fragment or a combination of non-opposing edge fragments, calculating an edge placement error of the selected edge fragment and proximally shifting the edge fragment until a quality limitation is met.
摘要翻译：本发明是一种迭代方法或程序，涉及一系列光学邻近校正（OPC）处理步骤，用于在光刻工艺期间精炼晶片上的集成电路设计布局。迭代方法可以应用为系统和计算机程序，以根据方向取向，选择边缘片段或非相对边缘片段的组合来分类和分组边缘片段，计算所选边缘片段的边缘放置误差和近端移动边缘片段直到满足质量限制。

10. 发明授权

US06242923B1 Method for detecting power plane-to-power plane shorts and I/O net-to power plane shorts in modules and printed circuit boards 失效
标题翻译：用于检测模块和印刷电路板中的电源平面到电源平面短路和I / O网络到电源平面短路的方法
公开(公告)号：US06242923B1
公开(公告)日：2001-06-05
申请号：US09116396
申请日：1998-07-16
申请人： Michael E. Scaman , Edward J. Yarmchuk , Arnold Halperin
发明人： Michael E. Scaman , Edward J. Yarmchuk , Arnold Halperin
IPC分类号： G01R3128
CPC分类号： G01R31/281 , G01R1/07314 , G01R31/025
摘要： A method of locating in a non-destructive and non-invasive manner power plane-to-power plane shorts or I/O net-to-power plane shorts found in a printed circuit board or a multi-chip-module by way of a magnetic field generating probe is described. Thousands of nets can be simultaneously tested to detect not only the presence of a short but also to accurately pinpoint its position. For high resistance shorts, the probe is provided with a pot core housed inductor located at its tip, and is used at low frequencies to minimize the effect of the capacitive impedance between the power planes. For low resistance shorts, the probe is used at high frequencies, delivering equal but opposite current to each of two matched inductors at the tip of the probe to maximize mutual inductive coupling while minimizing electrostatic capacitive coupling with the board or module. In both cases, the highest current stress is on the probe rather than on the expensive and fragile package under inspection. This allows the test to be both more sensitive to high resistance shorts at low frequencies and is less destructive, thereby being less likely to blow filamentary shorts due to high current stresses through the board or module.
摘要翻译：以非破坏性和非侵入性的方式定位在印刷电路板或多芯片模块中通过以下方式发现的平面到电源平面短路或I / O网络至电源平面短路的方法描述了磁场产生探针。可以同时测试数千个网络，以检测不仅存在短路，还可以准确地确定其位置。对于高电阻短路，探头设置有位于其尖端的锅芯容纳电感器，并且以低频率使用以最小化电力平面之间的电容性阻抗的影响。对于低电阻短路，探头以高频率使用，为探头顶端的两个匹配电感器中的每一个提供相等但相反的电流，以最大化互感耦合，同时最小化与电路板或模块的静电电容耦合。在这两种情况下，最高的电流应力在探头上，而不是昂贵和脆弱的被检查的包装。这允许测试在低频下对高电阻短路更敏感，并且具有较小的破坏性，因此由于通过电路板或模块的高电流应力而不太可能发生短路短路。

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