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1. 发明授权

US6160315A Copper alloy via structure 有权
标题翻译：铜合金通孔结构
公开(公告)号：US6160315A
公开(公告)日：2000-12-12
申请号：US478721
申请日：2000-01-06
申请人： Tony Chiang , Peijun Ding , Barry Chin , Imran Hashim , Bingxi Sun
发明人： Tony Chiang , Peijun Ding , Barry Chin , Imran Hashim , Bingxi Sun
IPC分类号： C23C14/02 , C23C14/16 , C23C16/02 , C23C16/06 , H01L21/285 , H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76834 , C23C14/024 , C23C14/025 , C23C14/16 , C23C14/165 , C23C16/0281 , C23C16/06 , H01L21/2855 , H01L21/76831 , H01L21/76843 , H01L21/76871 , H01L21/76877 , H01L21/76888 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A copper via structure formed when copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide but also extends into the oxide a distance of about 100 nm. The alloying metal oxide having a thickness of about 6 nm on the oxide sidewalls encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.
摘要翻译：当铜和少量的合金金属如镁或铝形成的铜通孔结构在其表面的至少一部分上被分散在具有氧化物的基底上。在沉积期间晶片保持在升高的温度下，或者溅射膜被退火而晶片不暴露于环境中。由于高温，合金金属扩散到表面。如果表面暴露于低的氧分压或接触二氧化硅，则镁或铝形成薄的稳定氧化物，但也延伸到氧化物中约100nm的距离。在氧化物侧壁上具有约6nm厚度的合金化金属氧化物封装铜层以提供阻挡铜迁移的屏障，以形成二氧化硅以上的粘合层，并且用作后续生长铜的种子层，例如，通过电镀。

2. 发明授权

US06387805B2 Copper alloy seed layer for copper metallization 失效
标题翻译：铜合金种子层用于铜金属化
公开(公告)号：US06387805B2
公开(公告)日：2002-05-14
申请号：US08878143
申请日：1997-06-18
申请人： Peijun Ding , Tony Chiang , Imran Hashim , Bingxi Sun , Barry Chin
发明人： Peijun Ding , Tony Chiang , Imran Hashim , Bingxi Sun , Barry Chin
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , C23C14/024 , C23C14/025 , C23C14/16 , C23C14/165 , C23C16/0281 , C23C16/06 , H01L21/2855 , H01L21/28556 , H01L21/76831 , H01L21/76834 , H01L21/76867 , H01L21/76871 , H01L21/76877 , H01L21/76888 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A copper metallization structure and its method of formation in which a layer of a copper alloy, such as Cu—Mg or Cu—Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.
摘要翻译：在铜合金层上沉积铜基金属化结构及其形成方法，其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。铜合金层用作种子或润湿层，用于随后用基本上纯的铜填充通孔和沟槽。优选地，铜合金在溅射过程中冷沉积，但是在纯铜层沉积期间或之后在单独的退火步骤中，温度升高到足够高以使铜合金的合金元素迁移到电介质层，并形成阻挡铜，以扩散到介电层中并穿过介电层。该屏障还促进了合金层对电介质层的粘附，从而形成了用于随后的铜全填充技术的优异的润湿和种子层。可以使用PVD，CVD或电/无电镀来完成合金衬里特征的填充。

3. 发明授权

US06066892A Copper alloy seed layer for copper metallization in an integrated circuit 失效
标题翻译：铜合金种子层用于集成电路中的铜金属化
公开(公告)号：US06066892A
公开(公告)日：2000-05-23
申请号：US79107
申请日：1998-05-14
申请人： Peijun Ding , Tony Chiang , Imran Hashim , Bingxi Sun , Barry Chin
发明人： Peijun Ding , Tony Chiang , Imran Hashim , Bingxi Sun , Barry Chin
IPC分类号： H01L21/28 , C23C14/02 , C23C14/16 , C23C16/02 , C23C16/06 , H01L21/203 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532 , H01L29/45
CPC分类号： H01L21/76843 , C23C14/024 , C23C14/025 , C23C14/16 , C23C14/165 , C23C16/0281 , C23C16/06 , H01L21/28556 , H01L21/76831 , H01L21/76834 , H01L21/76867 , H01L21/76871 , H01L21/76877 , H01L21/76888 , H01L23/53233 , H01L23/53238 , H01L21/2855 , H01L2924/0002
摘要： A copper metallization structure in which a layer of a copper alloy, such as Cu--Mg or Cu--Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferred examples of the alloying elements and their atomic alloying percentage include magnesium between 0.05 and 6% and aluminum between 0.05 and 0.3%. Further examples include boron, tantalum, tellurium, and titanium. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.
摘要翻译：在铜合金层上沉积铜基金属化结构，其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。铜合金层用作种子或润湿层，用于随后用基本上纯的铜填充通孔和沟槽。合金元素的优选实例及其原子合金化百分比包括0.05至6％的镁和0.05-0.3％的铝。其他实例包括硼，钽，碲和钛。优选地，铜合金在溅射过程中冷沉积，但是在纯铜层沉积期间或之后在单独的退火步骤中，温度升高到足够高以使铜合金的合金元素迁移到电介质层，并形成阻挡铜，以扩散到介电层中并穿过介电层。该屏障还促进了合金层对电介质层的粘附，从而形成了用于随后的铜全填充技术的优异的润湿和种子层。可以使用PVD，CVD或电/无电镀来完成合金衬里特征的填充。

4. 发明授权

US6037257A Sputter deposition and annealing of copper alloy metallization 失效
标题翻译：铜合金金属化溅射沉积和退火
公开(公告)号：US6037257A
公开(公告)日：2000-03-14
申请号：US853191
申请日：1997-05-08
申请人： Tony Chiang , Peijun Ding , Barry Chin , Imran Hashim , Bingxi Sun
发明人： Tony Chiang , Peijun Ding , Barry Chin , Imran Hashim , Bingxi Sun
IPC分类号： C23C14/02 , C23C14/16 , C23C16/02 , C23C16/06 , H01L21/285 , H01L21/768 , H01L23/532 , H01L21/4763 , H01L21/44 , H01L23/48
CPC分类号： H01L21/76834 , C23C14/024 , C23C14/025 , C23C14/16 , C23C14/165 , C23C16/0281 , C23C16/06 , H01L21/76831 , H01L21/76843 , H01L21/76871 , H01L21/76877 , H01L21/76888 , H01L23/53233 , H01L23/53238 , H01L21/2855 , H01L2924/0002
摘要： Copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide. The alloying metal oxide encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.
摘要翻译：将铜和少量合金化金属如镁或铝分散在其表面的至少一部分上具有氧化物的衬底上。在沉积期间晶片保持在升高的温度下，或者溅射膜被退火而晶片不暴露于环境中。由于高温，合金金属扩散到表面。如果表面暴露于低的氧分压或接触二氧化硅，则镁或铝形成薄的稳定的氧化物。合金化金属氧化物封装铜层以提供阻挡铜迁移的屏障，以形成二氧化硅以上的粘合层，并且作为例如通过电镀的铜的后续生长的种子层。

5. 发明授权

US06313033B1 Ionized metal plasma Ta, TaNx, W, and WNx liners for gate electrode applications 失效
标题翻译：用于栅电极应用的离子化金属等离子体Ta，TaNx，W和WNx衬垫
公开(公告)号：US06313033B1
公开(公告)日：2001-11-06
申请号：US09362923
申请日：1999-07-27
申请人： Tony Chiang , Bingxi Sun , Suraj Rengarajan , Peijun Ding , Barry Chin
发明人： Tony Chiang , Bingxi Sun , Suraj Rengarajan , Peijun Ding , Barry Chin
IPC分类号： H01L2144
CPC分类号： H01L27/1087 , H01L21/2855 , H01L21/76843 , H01L28/40 , H01L28/56 , H01L28/75
摘要： The invention provides a method for forming a microelectronic device comprising: forming a first electrode; depositing an adhesion layer over the first electrode utilizing high density plasma physical vapor deposition, wherein the adhesion layer comprises a material selected from Ta, TaNx, W, WNx, Ta/TaNx, W/WNx, and combinations thereof, depositing a dielectric layer over the adhesion layer; and forming a second electrode over the dielectric layer. The invention also provides a microelectronic device comprising: a first electrode; a second electrode; a dielectric layer disposed between the first and second electrodes; and an adhesion layer disposed between the first electrode and the dielectric layer, wherein the adhesion layer comprises a material selected from Ta, TaNx, W, WNx, Ta/TaNx, W/WNx, and combinations thereof.
摘要翻译：本发明提供一种形成微电子器件的方法，包括：形成第一电极; 使用高密度等离子体物理气相沉积在第一电极上沉积粘合层，其中粘合层包括选自Ta，TaNx，W，WNx，Ta / TaNx，W / WNx的材料及其组合，将介电层沉积在粘合层; 以及在所述电介质层上形成第二电极。本发明还提供了一种微电子器件，包括：第一电极; 第二电极; 设置在所述第一和第二电极之间的电介质层; 以及设置在第一电极和电介质层之间的粘合层，其中粘合层包括选自Ta，TaNx，W，WNx，Ta / TaNx，W / WNx的材料及其组合。

6. 发明授权

US06488823B1 Stress tunable tantalum and tantalum nitride films 失效
标题翻译：应力可调钽和氮化钽膜
公开(公告)号：US06488823B1
公开(公告)日：2002-12-03
申请号：US09423470
申请日：1999-11-04
申请人： Tony Chiang , Peijun Ding , Barry L. Chin , Bingxi Sun
发明人： Tony Chiang , Peijun Ding , Barry L. Chin , Bingxi Sun
IPC分类号： C23C1434
CPC分类号： C23C14/345 , C23C14/0036 , C23C14/0641 , C23C14/16 , C23C14/3492 , C23C14/358 , C23C14/5833 , H01L21/2855 , H01L21/76838 , H01L21/76841 , H01L21/76843 , H01L21/76862 , H01L21/76864 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure pertains to our discovery that residual stress residing in a tantalum film or tantalum nitride film can be controlled (tuned) during deposition by adjusting at least two particular process variables which have counteracting effects on the residual film stress. By tuning individual film stresses within a film stack, it is possible to balance stresses within the stack. Process variables of particular interest include: power to the sputtering target process chamber pressure (i.e., the concentration of various gases and ions present in the chamber); substrate DC offset bias voltage (typically an increase in the AC applied substrate bias power); power to an ionization source (typically a coil); and temperature of the substrate upon which the film is deposited. The process chamber pressure and the substrate offset bias most significantly affect the film tensile and compressive stress components, respectively. The most advantageous tuning of a sputtered film is achieved using high density plasma sputter deposition, which provides for particular control over the ion bombardment of the depositing film surface. When the tantalum or tantalum nitride film is deposited using high density plasma sputtering, power to the ionization source can be varied for stress tuning of the film. We have been able to reduce the residual stress in tantalum or tantalum nitride films deposited using high density plasma sputtering to between about 6×10+9 dynes/cm2 and about −6×10+9 dynes/cm2 using techniques described herein.
摘要翻译：本公开涉及我们的发现，即通过调节对剩余膜应力具有抵消作用的至少两个特定工艺变量，可以在沉积期间控制（调整）驻留在钽膜或氮化钽膜中的残余应力。通过调整薄膜叠层内的各个薄膜应力，可以平衡叠层内的应力。特别感兴趣的过程变量包括：溅射靶处理室压力的功率（即存在于室中的各种气体和离子的浓度）; 衬底DC偏移偏置电压（通常为施加衬底偏置功率的AC增加）; 电源（通常为线圈）; 以及沉积膜的基板的温度。处理室压力和基板偏移偏压分别最显着地影响膜的拉伸和压应力分量。使用高密度等离子体溅射沉积来实现溅射膜的最有利的调谐，其提供对沉积膜表面的离子轰击的特定控制。当使用高密度等离子体溅射沉积钽或氮化钽膜时，电离源的功率可以改变以用于膜的应力调谐。使用本文所述的技术，我们已经能够将使用高密度等离子体溅射沉积的钽或氮化钽膜中的残余应力减小到约6×10 9 + 9达因/ cm 2和约-6×10 9达因/ cm 2之间。

7. 发明授权

US06287977B1 Method and apparatus for forming improved metal interconnects 失效
标题翻译：用于形成改进的金属互连的方法和装置
公开(公告)号：US06287977B1
公开(公告)日：2001-09-11
申请号：US09126890
申请日：1998-07-31
申请人： Imran Hashim , Tony Chiang , Barry Chin
发明人： Imran Hashim , Tony Chiang , Barry Chin
IPC分类号： H01L21302
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.
摘要翻译：公开了形成没有通孔到通孔泄漏电流并具有低电阻的铜互连的方法。在第一方面，在铜氧化物溅射蚀刻之前，在第一金属层上沉积阻挡层，以防止铜原子到达层间电介质，并在其中形成通孔到漏电流路径。在第二方面，在溅射蚀刻之前，在第一金属层上沉积封盖电介质阻挡层。在溅射蚀刻期间，封盖电介质阻挡层重新分布在层间电介质的侧壁上，防止溅射蚀刻的铜原子到达层间电介质并在其中形成通孔到通孔泄漏路径。在第三方面，在溅射蚀刻之前，在第一金属层上沉积封盖介电阻挡层和阻挡层，以防止在溅射蚀刻期间产生的铜原子到达层间电介质并形成通孔到通孔泄漏路径其中。

8. 发明授权

US06992012B2 Method and apparatus for forming improved metal interconnects 失效
公开(公告)号：US06992012B2
公开(公告)日：2006-01-31
申请号：US10761466
申请日：2004-01-21
申请人： Imran Hashim , Tony Chiang , Barry Chin
发明人： Imran Hashim , Tony Chiang , Barry Chin
IPC分类号： H01L21/302
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

9. 发明授权

US06709987B2 Method and apparatus for forming improved metal interconnects 有权
公开(公告)号：US06709987B2
公开(公告)日：2004-03-23
申请号：US10067709
申请日：2002-02-05
申请人： Imran Hashim , Tony Chiang , Barry Chin
发明人： Imran Hashim , Tony Chiang , Barry Chin
IPC分类号： H01L21302
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

10. 发明授权

US06559061B2 Method and apparatus for forming improved metal interconnects 失效
公开(公告)号：US06559061B2
公开(公告)日：2003-05-06
申请号：US09928891
申请日：2001-08-13
申请人： Imran Hashim , Tony Chiang , Barry Chin
发明人： Imran Hashim , Tony Chiang , Barry Chin
IPC分类号： H01L21302
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76814 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

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