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1. 发明授权

US08051394B2 Yield evaluating apparatus and method thereof 有权
标题翻译：产量评价装置及其方法
公开(公告)号：US08051394B2
公开(公告)日：2011-11-01
申请号：US12264227
申请日：2008-11-03
申请人： Pei-Wen Luo , Jwu-E Chen , Chin-Long Wey , Liang-Chia Cheng , Ji-Jan Chen , Wen-Ching Wu
发明人： Pei-Wen Luo , Jwu-E Chen , Chin-Long Wey , Liang-Chia Cheng , Ji-Jan Chen , Wen-Ching Wu
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/5081 , G06F2217/10
摘要： A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.
摘要翻译：提供了一种产量评估装置及其方法。产量评估装置包括空间相关模块。空间相关模块接收至少一个处理相关数据和多个电路布局，并且根据处理相关数据获得电路布局中单元元件之间的相关系数。空间相关模块根据相关系数计算每个电路布局中的元件之间的空间相关性，并根据空间相关性选择一个电路布局。

2. 发明申请

US20100088655A1 YIELD EVALUATING APPARATUS AND METHOD THEREOF 有权
标题翻译： YIELD评估装置及其方法
公开(公告)号：US20100088655A1
公开(公告)日：2010-04-08
申请号：US12264227
申请日：2008-11-03
申请人： Pei-Wen Luo , Jwu-E Chen , Chin-Long Wey , Liang-Chia Cheng , Ji-Jan Chen , Wen-Ching Wu
发明人： Pei-Wen Luo , Jwu-E Chen , Chin-Long Wey , Liang-Chia Cheng , Ji-Jan Chen , Wen-Ching Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/10
摘要： A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.
摘要翻译：提供了一种产量评估装置及其方法。产量评估装置包括空间相关模块。空间相关模块接收至少一个处理相关数据和多个电路布局，并且根据处理相关数据获得电路布局中单元元件之间的相关系数。空间相关模块根据相关系数计算每个电路布局中的元件之间的空间相关性，并根据空间相关性选择一个电路布局。

3. 发明申请

US20080133990A1 Scan Test Data Compression Method And Decoding Apparatus For Multiple-Scan-Chain Designs 审中-公开
标题翻译：用于多扫描链设计的扫描测试数据压缩方法和解码设备
公开(公告)号：US20080133990A1
公开(公告)日：2008-06-05
申请号：US11672044
申请日：2007-02-07
申请人： Shih-Ping Lin , Chung-Len Lee , Jwu E. Chen , Ji-Jan Chen , Kun-Lun Luo , Wen-Ching Wu
发明人： Shih-Ping Lin , Chung-Len Lee , Jwu E. Chen , Ji-Jan Chen , Kun-Lun Luo , Wen-Ching Wu
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/3016 , G01R31/31727
摘要： Disclosed is a scan test data compression method and decoding apparatus for multiple-scan-chain designs. The apparatus comprises a on-chip decoder connected to a tester. The decoder includes a decoding buffer configured as a multilayer architecture, a controller, and a switching box for receiving a shift signal or a copy signal. The decoding buffer is used to store decoded test data. While the decoder decodes the encoded data, it transmits control signals to both the decoding buffer and the switching box from the controller, and sends the decoded data to scan chains of a CUT for testing through the decoding buffer. This invention has the advantages of simple encoding method, high compression rate, low power consumption in testing, and without the fault coverage loss.
摘要翻译：公开了一种用于多扫描链设计的扫描测试数据压缩方法和解码装置。该装置包括连接到测试器的片上解码器。解码器包括被配置为多层架构的解码缓冲器，控制器和用于接收移位信号或复制信号的开关盒。解码缓冲器用于存储解码的测试数据。当解码器解码编码数据时，它将控制信号从控制器发送到解码缓冲器和切换盒，并将解码的数据发送到CUT的扫描链，以通过解码缓冲器进行测试。本发明具有编码方式简单，压缩率高，测试功耗低，无故障覆盖损失的优点。

4. 发明授权

US06950046B2 IC with built-in self-test and design method thereof 有权
标题翻译： IC内置自检及其设计方法
公开(公告)号：US06950046B2
公开(公告)日：2005-09-27
申请号：US10894054
申请日：2004-07-20
申请人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
发明人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
IPC分类号： G01R31/28 , H03M1/10 , H03M3/00
CPC分类号： H03M3/378 , H03M3/458
摘要： IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.
摘要翻译： IC内置自检及其设计方法。 IC包括SD-ADC和Dft电路。 Dft电路使用数字刺激信号来解决片上模拟测试的死锁问题，并避免热噪声。此外，根据IC的设计方法，具有不同规格的电路可以使用Dft电路，而不会对原始SD-ADC造成性能下降。

5. 发明申请

US20050174273A1 IC WITH BUILT-IN SELF-TEST AND DESIGN METHOD THEREOF 有权
标题翻译： IC内置自检及其设计方法
公开(公告)号：US20050174273A1
公开(公告)日：2005-08-11
申请号：US10894054
申请日：2004-07-20
申请人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
发明人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
IPC分类号： G01R31/28 , H03M1/10 , H03M3/00
CPC分类号： H03M3/378 , H03M3/458
摘要： IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.
摘要翻译： IC内置自检及其设计方法。 IC包括SD-ADC和Dft电路。 Dft电路使用数字刺激信号来解决片上模拟测试的死锁问题，并避免热噪声。此外，根据IC的设计方法，具有不同规格的电路可以使用Dft电路，而不会对原始SD-ADC造成性能下降。

6. 发明申请

US20080076279A1 FOLDABLE ELECTRICAL CONNECTOR AND POWER SUPPLY APPARATUS HAVING SAME 有权
标题翻译：具有可折叠电气连接器和电源装置
公开(公告)号：US20080076279A1
公开(公告)日：2008-03-27
申请号：US11751767
申请日：2007-05-22
申请人： Wen-Ching Wu , Ya-Hui Chen
发明人： Wen-Ching Wu , Ya-Hui Chen
IPC分类号： H01R13/44
CPC分类号： H01R31/06
摘要： A power supply apparatus includes a main body, a first power connecting part and a foldable electrical connector. The main body includes a power converting circuit therein and has a first socket at a first side thereof. The first power connecting part has an end connected to the main body. The foldable electrical connector includes a housing and at least a conductive pin. The housing includes a connecting member and a receiving portion. The connecting member is electrically connected to the first socket of the main body. The conductive pin is disposed in the receiving portion and multi-angularly rotatable with respect to the housing so as to be selectively stored in the receiving portion or protruded from the housing.
摘要翻译：电源装置包括主体，第一电源连接部和可折叠的电连接器。主体在其中包括电力转换电路，并在其第一侧具有第一插座。第一电力连接部分的端部连接到主体。可折叠电连接器包括壳体和至少一个导电销。壳体包括连接构件和接收部分。连接构件电连接到主体的第一插座。导电销设置在接收部分中并相对于壳体多角度地旋转，以便选择性地存储在接收部分中或从壳体突出。

7. 发明授权

US06937106B2 Built-in jitter measurement circuit for voltage controlled oscillator and phase locked loop 有权
标题翻译：用于压控振荡器和锁相环的内置抖动测量电路
公开(公告)号：US06937106B2
公开(公告)日：2005-08-30
申请号：US10749560
申请日：2004-01-02
申请人： Yeong-Jar Chang , Shen-Tien Lin , Wen-Ching Wu , Kun-Lun Luo
发明人： Yeong-Jar Chang , Shen-Tien Lin , Wen-Ching Wu , Kun-Lun Luo
IPC分类号： G01R29/26 , H03L7/06 , G01R23/00
CPC分类号： G01R29/26 , H03L7/06
摘要： A built-in jitter measurement circuit for a VCO (voltage-controlled oscillator) and a PLL (phase-locked loop) is disclosed. The circuit includes a divider for dividing frequency of a signal, a time to digital converter (TDC) for converting the period of the divided signal into digital values, a variance calculator for calculating variance of the period of the divided signal, a mean calculator for calculating mean value of the period of the divided signal, a encoder and counter for encoding and calculating the period of the divided signal, and a state controller as a controller for all other components. The circuit disclosed utilizes output clock of an opened-loop circuit to be measured and a divider for increasing jitter of the original signal. By measuring the bandwidth of a closed-loop circuit, accordingly, jitter of output clock of an opened-loop or an closed-loop circuit is measured by correlating the measured bandwidth and the jitter values from extrapolation.
摘要翻译：公开了一种用于VCO（压控振荡器）和PLL（锁相环）的内置抖动测量电路。该电路包括用于分频信号的分频器，用于将分频信号的周期转换为数字值的时间数字转换器（TDC），用于计算分频信号周期的方差的方差计算器，用于计算分割信号的周期的平均值，用于编码和计算分频信号的周期的编码器和计数器，以及作为所有其他分量的控制器的状态控制器。所公开的电路利用要测量的开环电路的输出时钟和用于增加原始信号的抖动的分频器。通过测量闭环电路的带宽，相应地，通过将测量的带宽与来自外推的抖动值相关联来测量开环或闭环电路的输出时钟的抖动。

8. 发明申请

US20050116877A1 Antenna and fixed base rotary positioning structure 失效
标题翻译：天线和固定基座旋转定位结构
公开(公告)号：US20050116877A1
公开(公告)日：2005-06-02
申请号：US10724061
申请日：2003-12-01
申请人： Wen-Ching Wu
发明人： Wen-Ching Wu
IPC分类号： H01Q1/08 , H01Q3/02
CPC分类号： H01Q1/084
摘要： The present invention discloses an antenna with a fixed base rotary positioning structure, which can be placed on a table or hung on a wall, comprising: a fixed base; a protrusion disposed on the fixed base and having an open end on one side; a chamber enclosed by the rest of three sides; a pivotal axial hole and an arc groove being correspondingly disposed on both sides of the inner wall of the protrusion, such that the pivotal axial hole and the arc groove precisely and pivotally coupling the pivotal axis and the protruded fixing point to the two corresponding sides at one end of the antenna, and the antenna using such pivotal axis as the rotary axis to adjust the antenna to any angle by the open end of the protrusion.
摘要翻译：本发明公开了一种具有固定基座旋转定位结构的天线，其可以放置在桌子上或挂在墙上，包括：固定基座; 突出部，其设置在所述固定基座上并且在一侧具有开口端; 一个由三面其余三边围成的房间; 枢转轴孔和弧槽相应地设置在突起的内壁的两侧，使得枢转轴向孔和弧槽精确地并且枢转地将枢转轴线和突出的固定点联接到两个对应的侧面天线的一端和使用与旋转轴线相关的枢转轴线的天线，以通过突起的开口端将天线调整到任何角度。

9. 发明申请

US20050093511A1 Charger capable of providing illumination light 审中-公开
标题翻译：充电器能够提供照明灯
公开(公告)号：US20050093511A1
公开(公告)日：2005-05-05
申请号：US10840339
申请日：2004-05-06
申请人： Wen-Ching Wu
发明人： Wen-Ching Wu
IPC分类号： H02J7/00
CPC分类号： H05B37/02
摘要： A charger capable of providing illumination light is disclosed. The charger comprises a main body to be coupled with a power source for charging an electronic apparatus, an illumination device disposed on the main body for providing illumination light, and a control switch disposed on the main body and electrically coupled with the illumination device for controlling the illumination device to illuminate light.
摘要翻译：公开了一种能够提供照明光的充电器。充电器包括与电子设备充电的电源耦合的主体，设置在主体上用于提供照明光的照明装置，以及设置在主体上并与照明装置电连接以控制的照明装置照明装置照亮光。

10. 发明申请

US20050006083A1 Temperature-homogenizing device 有权
标题翻译：温度均化装置
公开(公告)号：US20050006083A1
公开(公告)日：2005-01-13
申请号：US10756064
申请日：2004-01-13
申请人： Yin-Yuan Chen , Wen-Ching Wu , Jui-Yuan Hsu
发明人： Yin-Yuan Chen , Wen-Ching Wu , Jui-Yuan Hsu
IPC分类号： H01L23/36 , H01L23/433 , H05K7/20
CPC分类号： H05K7/20436 , H01L23/36 , H01L23/433 , H01L2924/0002 , H05K7/20481 , H01L2924/00
摘要： A temperature-homogenizing device for uniformly dissipating heat generated from electronic components in an electronic device to a housing of the electronic device includes a first and a second higher thermally conductive layers and a first lower thermally conductive layer. The first lower thermally conductive layer is disposed between the first and the second higher thermally conductive layers, and made of a material or a medium having a lower thermal conductivity than each of the first and the second higher thermally conductive layers. By means of this temperature-homogenizing device, the heat is homogeneously distributed throughout the first and the second higher thermally conductive layers at a higher thermal conduction rate and transferred through the first lower thermally conductive layer at a lower thermal conduction rate so as to maintain homogeneous temperature distribution on the housing.
摘要翻译：用于将电子设备中的电子部件产生的热量均匀地散发到电子设备的壳体的温度均化装置包括第一和第二较高导热层和第一下部导热层。第一下部导热层设置在第一和第二较高导热层之间，并且由具有比每个第一和第二较高导热层的导热性低的材料或介质制成。通过该温度均化装置，热量以更高的热传导速率均匀地分布在第一和第二较高的导热层中，并以较低的热传导速率转移通过第一较低导热层，以保持均匀温度分布在房屋上。

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