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1. 发明授权

US06950046B2 IC with built-in self-test and design method thereof 有权
标题翻译： IC内置自检及其设计方法
公开(公告)号：US06950046B2
公开(公告)日：2005-09-27
申请号：US10894054
申请日：2004-07-20
申请人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
发明人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
IPC分类号： G01R31/28 , H03M1/10 , H03M3/00
CPC分类号： H03M3/378 , H03M3/458
摘要： IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.
摘要翻译： IC内置自检及其设计方法。 IC包括SD-ADC和Dft电路。 Dft电路使用数字刺激信号来解决片上模拟测试的死锁问题，并避免热噪声。此外，根据IC的设计方法，具有不同规格的电路可以使用Dft电路，而不会对原始SD-ADC造成性能下降。

2. 发明申请

US20050174273A1 IC WITH BUILT-IN SELF-TEST AND DESIGN METHOD THEREOF 有权
标题翻译： IC内置自检及其设计方法
公开(公告)号：US20050174273A1
公开(公告)日：2005-08-11
申请号：US10894054
申请日：2004-07-20
申请人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
发明人： Pei-Wen Luo , Yeong-Jar Chang , Jung-Chi Ho , Wen-Ching Wu
IPC分类号： G01R31/28 , H03M1/10 , H03M3/00
CPC分类号： H03M3/378 , H03M3/458
摘要： IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.
摘要翻译： IC内置自检及其设计方法。 IC包括SD-ADC和Dft电路。 Dft电路使用数字刺激信号来解决片上模拟测试的死锁问题，并避免热噪声。此外，根据IC的设计方法，具有不同规格的电路可以使用Dft电路，而不会对原始SD-ADC造成性能下降。

3. 发明申请

US20060156104A1 Wrapper testing circuits and method thereof for system-on-a-chip 审中-公开
标题翻译：包装机测试电路及其在片上系统的方法
公开(公告)号：US20060156104A1
公开(公告)日：2006-07-13
申请号：US11140745
申请日：2005-06-01
申请人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
发明人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
IPC分类号： G01R31/28
CPC分类号： G01R31/318555
摘要： A wrapper testing circuit and method thereof for System-On-a-Chip is provided for electrical tests of core circuits of an integrated circuit. The testing circuit includes a decoding logic with an encoding table for receiving test signals and delivering control signals in response to the test signals according to the table; a plurality of registers for saving the control signals temporarily and delivering the control signals to the core circuits; a bypass circuit for delivering the test signals; and an instruction register for saving the test signals temporarily and refreshing the data in the registers and the bypass circuits after the decoding logic issues the control signals. The encoding of the control signals is completed in one period. Compared with the serial encoding in the prior art, test time is reduced.
摘要翻译：提供了一种用于片上系统的封装测试电路及其方法，用于集成电路的核心电路的电气测试。测试电路包括具有编码表的解码逻辑，用于接收测试信号并根据该表响应于测试信号传递控制信号; 多个寄存器，用于暂时保存控制信号并将控制信号传送到核心电路; 用于传递测试信号的旁路电路; 以及在解码逻辑发出控制信号之后暂时保存测试信号并刷新寄存器和旁路电路中的数据的指令寄存器。控制信号的编码在一个周期内完成。与现有技术的串行编码相比，测试时间缩短。

4. 发明申请

US20070255986A1 Wrapper testing circuits and method thereof for system-on-a-chip 有权
标题翻译：包装机测试电路及其在片上系统的方法
公开(公告)号：US20070255986A1
公开(公告)日：2007-11-01
申请号：US11819464
申请日：2007-06-27
申请人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
发明人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
IPC分类号： G01R31/28
CPC分类号： G01R31/318555
摘要： A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs control signals and test signals and receives result signals executed by the core circuit. The wrapper testing circuit comprises a decoding logic and a plurality of wrapper boundary registers. The decoding logic has a signal decoding table which receives and decodes the control signals and then issues decoded signals according to the signal decoding table. The WBR shifts, updates and captures the test signals for the core circuit to execute and output the result signals according to the decoded signals. In comparison with prior art, the testing time is reduced.
摘要翻译：提供了一种用于至少集成电路的核心电路的电测试的片上系统的封装测试电路及其包装测试方法。控制器输出控制信号和测试信号并接收由核心电路执行的结果信号。包装测试电路包括解码逻辑和多个封装边界寄存器。解码逻辑具有信号解码表，其接收并解码控制信号，然后根据信号解码表发出解码信号。 WBR移位，更新和捕获核心电路的测试信号，以根据解码的信号执行和输出结果信号。与现有技术相比，测试时间缩短。

5. 发明申请

US20060064618A1 Method and apparatus of build-in self-diagnosis and repair in a memory with syndrome identification 有权
标题翻译：在具有综合征鉴定的记忆中建立自我诊断和修复的方法和装置
公开(公告)号：US20060064618A1
公开(公告)日：2006-03-23
申请号：US11001345
申请日：2004-11-30
申请人： Cheng-Wen Wu , Rei-Fu Huang , Chin-Lung Su , Wen-Ching Wu , Yeong-Jar Chang , Kun-Lun Luo , Shen-Tien Lin
发明人： Cheng-Wen Wu , Rei-Fu Huang , Chin-Lung Su , Wen-Ching Wu , Yeong-Jar Chang , Kun-Lun Luo , Shen-Tien Lin
IPC分类号： G01R31/28
CPC分类号： G11C29/4401 , G11C29/16 , G11C29/44 , G11C29/72 , G11C2029/0405 , G11C2029/3602
摘要： The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.
摘要翻译：本发明提供一种存储器建立自诊断和修复的方法和装置，其具有综合征识别。它在测试过程中使用故障模式识别和故障排序格式结构来识别存储器中的故障行，故障列和单个故障字，然后输出故障信息。基于综合信息，应用冗余分析算法来分配修复故障存储单元的备用存储单元。它具有具有增强的故障综合征识别的定序器，具有改进的冗余利用率的内置冗余分析电路，以及在正常访问期间减少定时损失的地址可重构电路。本发明减少了自动测试设备中的占用时间和所需的捕获存储空间。它还增加了修复率，并减少了所需的面积开销。

6. 发明授权

US06937106B2 Built-in jitter measurement circuit for voltage controlled oscillator and phase locked loop 有权
标题翻译：用于压控振荡器和锁相环的内置抖动测量电路
公开(公告)号：US06937106B2
公开(公告)日：2005-08-30
申请号：US10749560
申请日：2004-01-02
申请人： Yeong-Jar Chang , Shen-Tien Lin , Wen-Ching Wu , Kun-Lun Luo
发明人： Yeong-Jar Chang , Shen-Tien Lin , Wen-Ching Wu , Kun-Lun Luo
IPC分类号： G01R29/26 , H03L7/06 , G01R23/00
CPC分类号： G01R29/26 , H03L7/06
摘要： A built-in jitter measurement circuit for a VCO (voltage-controlled oscillator) and a PLL (phase-locked loop) is disclosed. The circuit includes a divider for dividing frequency of a signal, a time to digital converter (TDC) for converting the period of the divided signal into digital values, a variance calculator for calculating variance of the period of the divided signal, a mean calculator for calculating mean value of the period of the divided signal, a encoder and counter for encoding and calculating the period of the divided signal, and a state controller as a controller for all other components. The circuit disclosed utilizes output clock of an opened-loop circuit to be measured and a divider for increasing jitter of the original signal. By measuring the bandwidth of a closed-loop circuit, accordingly, jitter of output clock of an opened-loop or an closed-loop circuit is measured by correlating the measured bandwidth and the jitter values from extrapolation.
摘要翻译：公开了一种用于VCO（压控振荡器）和PLL（锁相环）的内置抖动测量电路。该电路包括用于分频信号的分频器，用于将分频信号的周期转换为数字值的时间数字转换器（TDC），用于计算分频信号周期的方差的方差计算器，用于计算分割信号的周期的平均值，用于编码和计算分频信号的周期的编码器和计数器，以及作为所有其他分量的控制器的状态控制器。所公开的电路利用要测量的开环电路的输出时钟和用于增加原始信号的抖动的分频器。通过测量闭环电路的带宽，相应地，通过将测量的带宽与来自外推的抖动值相关联来测量开环或闭环电路的输出时钟的抖动。

7. 发明授权

US07506231B2 Wrapper testing circuits and method thereof for system-on-a-chip 有权
标题翻译：包装机测试电路及其在片上系统的方法
公开(公告)号：US07506231B2
公开(公告)日：2009-03-17
申请号：US11819464
申请日：2007-06-27
申请人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
发明人： Yeong-Jar Chang , Wen-Ching Wu , Kun-Lun Luo , Chia-Jen Lee
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G01R31/318555
摘要： A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs control signals and test signals and receives result signals executed by the core circuit. The wrapper testing circuit comprises a decoding logic and a plurality of wrapper boundary registers. The decoding logic has a signal decoding table which receives and decodes the control signals and then issues decoded signals according to the signal decoding table. The WBR shifts, updates and captures the test signals for the core circuit to execute and output the result signals according to the decoded signals. In comparison with prior art, the testing time is reduced.
摘要翻译：提供了一种用于至少集成电路的核心电路的电测试的片上系统的封装测试电路及其包装测试方法。控制器输出控制信号和测试信号并接收由核心电路执行的结果信号。包装测试电路包括解码逻辑和多个封装边界寄存器。解码逻辑具有信号解码表，其接收并解码控制信号，然后根据信号解码表发出解码信号。 WBR移位，更新和捕获核心电路的测试信号，以根据解码的信号执行和输出结果信号。与现有技术相比，测试时间缩短。

8. 发明授权

US07228468B2 Method and apparatus of build-in self-diagnosis and repair in a memory with syndrome identification 有权
标题翻译：在具有综合征鉴定的记忆中建立自我诊断和修复的方法和装置
公开(公告)号：US07228468B2
公开(公告)日：2007-06-05
申请号：US11001345
申请日：2004-11-30
申请人： Cheng-Wen Wu , Rei-Fu Huang , Chin-Lung Su , Wen-Ching Wu , Yeong-Jar Chang , Kun-Lun Luo , Shen-Tien Lin
发明人： Cheng-Wen Wu , Rei-Fu Huang , Chin-Lung Su , Wen-Ching Wu , Yeong-Jar Chang , Kun-Lun Luo , Shen-Tien Lin
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/16 , G11C29/44 , G11C29/72 , G11C2029/0405 , G11C2029/3602
摘要： The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.
摘要翻译：本发明提供一种存储器建立自诊断和修复的方法和装置，其具有综合征识别。它在测试过程中使用故障模式识别和故障排序格式结构来识别存储器中的故障行，故障列和单个故障字，然后输出故障信息。基于综合信息，应用冗余分析算法来分配修复故障存储单元的备用存储单元。它具有具有增强的故障综合征识别的定序器，具有改进的冗余利用率的内置冗余分析电路，以及在正常访问期间减少定时损失的地址可重新配置电路。本发明减少了自动测试设备中的占用时间和所需的捕获存储空间。它还增加了修复率，并减少了所需的面积开销。

9. 发明申请

US20050057312A1 Built-in jitter measurement circuit for voltage controlled oscillator and phase locked loop 有权
公开(公告)号：US20050057312A1
公开(公告)日：2005-03-17
申请号：US10749560
申请日：2004-01-02
申请人： Yeong-Jar Chang , Shen-Tien Lin , Wen-Ching Wu , Kun-Lun Luo
发明人： Yeong-Jar Chang , Shen-Tien Lin , Wen-Ching Wu , Kun-Lun Luo
IPC分类号： G01R29/26 , H03L7/06 , H03L7/00
CPC分类号： G01R29/26 , H03L7/06
摘要： A built-in jitter measurement circuit for a VCO (voltage-controlled oscillator) and a PLL (phase-locked loop) is disclosed. The circuit includes a divider for dividing frequency of a signal, a time to digital converter (TDC) for converting the period of the divided signal into digital values, a variance calculator for calculating variance of the period of the divided signal, a mean calculator for calculating mean value of the period of the divided signal, a encoder and counter for encoding and calculating the period of the divided signal, and a state controller as a controller for all other components. The circuit disclosed utilizes output clock of an opened-loop circuit to be measured and a divider for increasing jitter of the original signal. By measuring the bandwidth of a closed-loop circuit, accordingly, jitter of output clock of an opened-loop or an closed-loop circuit is measured by correlating the measured bandwidth and the jitter values from extrapolation.

10. 发明授权

US07945404B2 Clock jitter measurement circuit and integrated circuit having the same 有权
标题翻译：时钟抖动测量电路和集成电路相同
公开(公告)号：US07945404B2
公开(公告)日：2011-05-17
申请号：US12108796
申请日：2008-04-24
申请人： Jung-Chi Ho , Sheng-Bin Lin , Yeong-Jar Chang
发明人： Jung-Chi Ho , Sheng-Bin Lin , Yeong-Jar Chang
IPC分类号： G01R23/00 , G06F19/00
CPC分类号： G01R29/26 , G01R31/3016 , G01R31/31709
摘要： Provided is a measurement circuit for measuring a jitter of a clock signal. Delay elements delay the clock signal into delayed clock signal. Latches latch the delayed clock signals to indicate whether transition edges of the clock signal is within a window value which is corresponding to delays of the delay elements. Based on the latch result from the latches, a finite state machine generates control signals for controlling the delay elements. If the latch result indicates that the transition edges of the clock signal is not within the window value, the control signals adjust the delays of the delay elements and the window value. The jitter of the clock signal is measured based on the delays of the delay elements and the window value.
摘要翻译：提供了一种用于测量时钟信号的抖动的测量电路。延迟元件将时钟信号延迟到延迟的时钟信号。锁存器锁存延迟的时钟信号以指示时钟信号的转换边沿是否在对应于延迟元件的延迟的窗口值内。基于锁存器的锁存结果，有限状态机产生用于控制延迟元件的控制信号。如果锁存结果指示时钟信号的转换边缘不在窗口值内，则控制信号调整延迟元件的延迟和窗口值。基于延迟元件的延迟和窗口值来测量时钟信号的抖动。

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