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1. 发明授权

US07167392B1 Non-volatile memory cell with improved programming technique 有权
标题翻译：具有改进编程技术的非易失性存储单元
公开(公告)号：US07167392B1
公开(公告)日：2007-01-23
申请号：US11183198
申请日：2005-07-15
申请人： Pavel Poplevine , Annie-Li-Keow Lum , Hengyang Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Annie-Li-Keow Lum , Hengyang Lin , Andrew J. Franklin
IPC分类号： G11C11/34 , G11C14/00 , G11C16/04
CPC分类号： G11C14/00 , G11C7/06 , G11C16/0408
摘要： A non-volatile memory (NVM) cell splits its basic function, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each function. The cell structure also includes an embedded static random access memory (SRAM) cell that utilizes a latch structure to preprogram data to be written to the cell. The programming method for the cell utilizes a reverse Fowler-Nordheim tunneling mechanism with a very small programming current, allowing an entire NVM array to be programmed at one cycle.
摘要翻译：非易失性存储器（NVM）单元在四个PMOS晶体管结构中分离其基本功能，即编程，擦除，读取和控制，允许每个功能的独立优化。单元结构还包括嵌入式静态随机存取存储器（SRAM）单元，其利用锁存结构来预编程要写入单元的数据。该单元的编程方法利用具有非常小的编程电流的反向Fowler-Nordheim隧道机制，允许在一个周期对整个NVM阵列进行编程。

2. 发明授权

US07286383B1 Bit line sharing and word line load reduction for low AC power SRAM architecture 有权
标题翻译：低交流电源SRAM架构的位线共享和字线负载降低
公开(公告)号：US07286383B1
公开(公告)日：2007-10-23
申请号：US10215676
申请日：2002-08-10
申请人： Pavel Poplevine , Annie-Li-Koow Lum , Hengyang Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Annie-Li-Koow Lum , Hengyang Lin , Andrew J. Franklin
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C8/08 , G11C11/412 , G11C11/413 , G11C2207/002 , G11C2207/2227
摘要： In a SRAM structure, space and power saving is achieved by providing row and column select lines to select a specific bit cell, and reducing the number of bit lines in the structure used for writing to and reading from the bit cells. The number of bit lines is reduced by sharing bit lines of adjacent bit cells. Furthermore, in order to achieve power saving, the load on the row select lines is reduced by sharing the pass gates between adjacent bit cells that are used to control precharging, reading from and writing to the bit cells.
摘要翻译：在SRAM结构中，通过提供行和列选择线来选择特定位单元并减少用于写入和从位单元读取的结构中的位线的数量来实现空间和功率节省。通过共享相邻位单元的位线来减少位线的数量。此外，为了实现省电，通过共享用于控制预充电，从位单元读取和向位单元写入的相邻位单元之间的通过门，减少了行选择线上的负载。

3. 发明授权

US07164606B1 Reverse fowler-nordheim tunneling programming for non-volatile memory cell 有权
标题翻译：用于非易失性存储单元的反向fowler-nordheim隧道编程
公开(公告)号：US07164606B1
公开(公告)日：2007-01-16
申请号：US11182115
申请日：2005-07-15
申请人： Pavel Poplevine , Hengyang Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Hengyang Lin , Andrew J. Franklin
IPC分类号： G11C16/12
CPC分类号： G11C16/0441
摘要： In accordance with a method of programming an NVM array that includes 4-transistor PMOS non-volatile memory (NVM) cells having commonly connected floating gates, for all the cell's in the array that are to be programmed, all the electrodes of the cell are grounded. Then, an inhibiting voltage Vn is applied to the bulk-connected source region Vr of the cell's read transistor Pr, to the commonly connected drain, bulk and source regions Ve of the cell's erase transistor Pe, and to the drain region Dr of the read transistor Pr. The source region Vp and the drain region Dp of the cell's programming transistor Pw are grounded. The bulk Vnw of the programming transistor Pw is optional; it can be grounded or remain at the inhibiting voltage Vn. For all cells in the NVM array that are not selected for programming, the inhibiting voltage Vn is applied to Vr, Ve and Dr and is also applied to Vp, Dp and Vnw. The control gate voltage Vc of the cell's control transistor Pc is then swept from 0V to a maximum programming voltage Vcmax in a programming time Tprog. The control gate voltage Vc is then ramped down from the maximum programming voltage Vcmax to 0V. All electrodes of the cell and the inhibiting voltage Vn are then returned to ground.
摘要翻译：根据一种对包括具有共同连接的浮动栅极的4晶体管PMOS非易失性存储器（NVM）单元的NVM阵列进行编程的方法，对于要编程的阵列中的所有单元，单元的所有电极均为接地然后，将抑制电压Vn施加到单元读取晶体管Pr的体连接源极区域Vr到单元的擦除晶体管Pe的共同连接的漏极，体积和源极区域Ve以及读取的晶体管的漏极区域Dr 晶体管Pr。单元编程晶体管Pw的源极区域Vp和漏极区域Dp接地。编程晶体管Pw的体积Vnw是可选的; 它可以接地或保持在抑制电压Vn。对于未选择编程的NVM阵列中的所有单元，将抑制电压Vn施加到Vr，Ve和Dr，并且也施加到Vp，Dp和Vnw。然后，在编程时间Tprog中，电池控制晶体管Pc的控制栅极电压Vc从0V扫描到最大编程电压Vcmax。然后控制栅极电压Vc从最大编程电压Vcmax下降到0V。然后电池的所有电极和抑制电压Vn返回到地面。

4. 发明授权

US07061792B1 Low AC power SRAM architecture 有权
标题翻译：低交流电源SRAM架构
公开(公告)号：US07061792B1
公开(公告)日：2006-06-13
申请号：US10215678
申请日：2002-08-10
申请人： Pavel Poplevine , Annie-Li-Keow Lum , Hengyang Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Annie-Li-Keow Lum , Hengyang Lin , Andrew J. Franklin
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C11/412 , G11C7/18 , G11C2207/002
摘要： In a SRAM structure, power consumption is reduced by providing a structure which allows specific memory cells to be selected using word lines and column select lines, and reducing the load on the column address lines by dividing the load into sectors. The dividing into sectors is achieved by making use of sector select lines for selecting two or more rows of cells, and logically ANDing the sector select lines with the column select lines.
摘要翻译：在SRAM结构中，通过提供允许使用字线和列选择线选择特定存储器单元的结构来降低功耗，并且通过将负载分成扇区来减少列地址线的负载。通过使用用于选择两行或多行单元的扇区选择线以及逻辑地将扇区选择线与列选择线进行逻辑运算来实现划分为扇区。

5. 发明授权

US07239558B1 Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle 有权
标题翻译：在单个周期中对非易失性存储器（NVM）单元阵列进行热电子注入编程的方法
公开(公告)号：US07239558B1
公开(公告)日：2007-07-03
申请号：US11235834
申请日：2005-09-26
申请人： Pavel Poplevine , Annie-Li-Keow Lum , Hengyang Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Annie-Li-Keow Lum , Hengyang Lin , Andrew J. Franklin
IPC分类号： G11C11/34
CPC分类号： G11C11/005 , G11C14/00 , G11C16/0441
摘要： A non-volatile memory (NVM) cell splits its basic functions, i.e. program, erase, read and control, among a four PMOS transistor structure, allowing independent optimization of each cell function. The cell structure also includes an embedded static random access memory (SRAM) cell that utilizes a latch structure to preprogram data to be written to the cell and a plurality of cascoded NMOS pass gates. The cell structure reduces total programming time and provides the flexibility of programming the entire cell array simultaneously or one row or sector of the array at a time.
摘要翻译：非易失性存储器（NVM）单元在四个PMOS晶体管结构中分离其基本功能，即编程，擦除，读取和控制，允许每个单元功能的独立优化。单元结构还包括嵌入式静态随机存取存储器（SRAM）单元，其利用锁存结构来预编程要写入单元的数据和多个级联的NMOS通道门。单元结构减少总编程时间，并提供同时编程整个单元阵列或阵列的一行或多个扇区的灵活性。

6. 发明授权

US06642587B1 High density ROM architecture 有权
标题翻译：高密度ROM架构
公开(公告)号：US06642587B1
公开(公告)日：2003-11-04
申请号：US10214021
申请日：2002-08-07
申请人： Pavel Poplevine , Hengyang Lin , Andrew J. Franklin , Ernes Ho
发明人： Pavel Poplevine , Hengyang Lin , Andrew J. Franklin , Ernes Ho
IPC分类号： H01L2976
CPC分类号： H01L27/11246 , G11C17/123 , H01L27/112
摘要： A ROM array which provides for reduced size and power consumption. The bit cell of the ROM provides that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed. Further, where a bit cell does not provide a transistor between the bit line and the word line a bit cell region in the substrate can consist substantially of an isolating dielectric material.
摘要翻译：提供减小尺寸和功耗的ROM阵列。 ROM的位单元提供了当晶体管设置在位线和字线之间时，第一类型的信息被存储在位单元中，并且第二类型的信息被存储在单元中，当没有晶体管设置在单元之间时位线和字线。在晶体管形成在位线和字线之间的情况下，在位单元中提供位线和可以在衬底中形成晶体管漏极的区域之间的接触。在位单元在字线和位线之间不提供晶体管的情况下，在位线和可以形成晶体管漏极的区域之间不提供接触。此外，在位单元不在位线和字线之间提供晶体管的情况下，衬底中的位单元区域可以基本上由隔离电介质材料组成。

7. 发明授权

US06563730B1 Low power static RAM architecture 有权
标题翻译：低功耗静态RAM架构
公开(公告)号：US06563730B1
公开(公告)日：2003-05-13
申请号：US10119191
申请日：2002-04-09
申请人： Pavel Poplevine , Hengyang Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Hengyang Lin , Andrew J. Franklin
IPC分类号： G11C1100
CPC分类号： G11C11/419 , G11C11/412
摘要： A static RAM bit cell and a system and method for operating an array of such static RAM bit cells. The static RAM bit cell herein includes a cell of four transistors configured to store data. It also includes a pair of word line pass transistors and a pair of column pass transistors coupled to the cell of four transistors. The word line pass transistors are coupled to a word line such that they can be opened in closed in response to a signal on the word line. The column pass transistors are coupled to a column select transistor such that they can be opened and closed in response to a signal on the column select line. Using this configuration signals can be generated on the word line and the column select line so that only a small fraction of the total number of static RAM bit cells in an array need to be charged and discharged in connection with performing read and write operations to a specific static RAM bit cell.
摘要翻译：静态RAM位单元以及用于操作这种静态RAM位单元阵列的系统和方法。这里的静态RAM比特单元包括被配置为存储数据的四个晶体管的单元。它还包括一对字线传输晶体管和耦合到四个晶体管的单元的一对列传输晶体管。字线传输晶体管耦合到字线，使得它们可以响应于字线上的信号而在闭合时打开。列通晶体管耦合到列选择晶体管，使得它们可以响应于列选择线上的信号而被打开和关闭。使用该配置可以在字线和列选择线上生成信号，使得阵列中的静态RAM位单元的总数中只有一小部分需要对执行读和写操作进行充电和放电特定的静态RAM位元。

8. 发明授权

US07126866B1 Low power ROM architecture 有权
标题翻译：低功耗ROM架构
公开(公告)号：US07126866B1
公开(公告)日：2006-10-24
申请号：US10215699
申请日：2002-08-10
申请人： Pavel Poplevine , Ernes Ho , Hengyang Lin , Andrew J. Franklin
发明人： Pavel Poplevine , Ernes Ho , Hengyang Lin , Andrew J. Franklin
IPC分类号： G11C7/00
CPC分类号： G11C17/12 , G11C7/12
摘要： In a ROM structure, power consumption is reduced by providing for pre-discharging of only the bit line corresponding to the memory location that is being read. Column select lines are coupled to logic to switch in a pre-discharging circuit prior to reading, and to disconnect, from the pre-discharging circuit during reading, only the bit line corresponding to the memory location being read.
摘要翻译：在ROM结构中，通过仅对与正在读取的存储器位置相对应的位线进行预放电来降低功耗。列选择线耦合到逻辑以在读取之前切换预放电电路，并且在读取期间从预放电电路断开，仅读取对应于存储器位置的位线。

9. 发明授权

US06618282B1 High density ROM architecture with inversion of programming 有权
标题翻译：高密度ROM架构与编程反演
公开(公告)号：US06618282B1
公开(公告)日：2003-09-09
申请号：US10213845
申请日：2002-08-07
申请人： Pavel Poplevine , Hengyang Lin , Andrew J. Franklin , Umer Ahmed Khan
发明人： Pavel Poplevine , Hengyang Lin , Andrew J. Franklin , Umer Ahmed Khan
IPC分类号： G11C1700
CPC分类号： G11C7/106 , G11C7/1012 , G11C7/1051 , G11C17/12
摘要： A ROM system which provides for reduced size and power consumption. This ROM systems allows for inverting the programming and sensing of information in bit cells of the ROM to reduce the number of transistors in bit cells of the ROM. Further bit cells of the ROM provide that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed.
摘要翻译：一种提供减小尺寸和功耗的ROM系统。该ROM系统允许反转ROM的位单元中的信息的编程和感测以减少ROM的位单元中的晶体管的数量。 ROM的其它位单元提供了当晶体管设置在位线和字线之间时，第一类型的信息被存储在位单元中，并且当第二类型的信息在位线和字线。在晶体管形成在位线和字线之间的情况下，在位单元中提供位线和可以在衬底中形成晶体管漏极的区域之间的接触。在位单元在字线和位线之间不提供晶体管的情况下，在位线和可以形成晶体管漏极的区域之间不提供接触。

10. 发明授权

US07863644B1 Bipolar transistor and method of forming the bipolar transistor with a backside contact 有权
标题翻译：双极晶体管和形成具有背面接触的双极晶体管的方法
公开(公告)号：US07863644B1
公开(公告)日：2011-01-04
申请号：US11786018
申请日：2007-04-09
申请人： Visvamohan Yegnashankaran , Hengyang Lin
发明人： Visvamohan Yegnashankaran , Hengyang Lin
IPC分类号： H01L27/082
CPC分类号： H01L29/7327 , H01L21/743 , H01L21/76898 , H01L21/8221 , H01L21/82285 , H01L23/481 , H01L27/0688 , H01L27/0826 , H01L29/41708 , H01L29/6628 , H01L2224/131 , H01L2924/1305 , H01L2924/014 , H01L2924/00
摘要： NPN and PNP bipolar junction transistors are formed on a wafer in a fabrication process that eliminates the heavily-doped buried layers and the lightly-doped epitaxial layer by forming back side collector contacts that are electrically connected to an interconnect structure on the top side of the wafer with through-the-wafer contacts.
摘要翻译：在制造工艺中在晶片上形成NPN和PNP双极结型晶体管，其通过形成背面侧集电极触点而消除重掺杂掩埋层和轻掺杂外延层，所述后侧集电极触点电连接到位于晶圆与晶圆接触。

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