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1. 发明授权

US06448606B1 Semiconductor with increased gate coupling coefficient 有权
标题翻译：半导体具有增加的栅极耦合系数
公开(公告)号：US06448606B1
公开(公告)日：2002-09-10
申请号：US09513261
申请日：2000-02-24
申请人： Allen S. Yu , Thomas C. Scholer , Paul J. Steffan
发明人： Allen S. Yu , Thomas C. Scholer , Paul J. Steffan
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A reduced device geometry semiconductor memory device is provided which has increased device efficiency because of an increased gate coupling coefficient. Shallow trench isolations are formed in a semiconductor substrate. The shallow trench isolations are selectively shaped in order to form a control gate dielectric layer later with a large width relative to the width between the floating gates.
摘要翻译：提供了一种缩小的器件几何形状半导体存储器件，其由于增加的栅极耦合系数而具有增加的器件效率。在半导体衬底中形成浅沟槽隔离。浅沟槽隔离件被选择成形以便稍后形成相对于浮动栅极之间宽度的大宽度的控制栅极电介质层。

2. 发明授权

US06395567B1 Process control using ideal die data in an optical comparator scanning system 失效
标题翻译：在光学比较器扫描系统中使用理想的裸片数据进行过程控制
公开(公告)号：US06395567B1
公开(公告)日：2002-05-28
申请号：US09109114
申请日：1998-07-02
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G01R3126
CPC分类号： G01N21/95607 , G01N21/9501 , G01R31/311
摘要： A method of detecting defects on dice in semiconductor wafer wherein each dice in a layer is scanned and data from each dice is compared to data collected from an ideal dice obtained from the same level on a pre-production wafer. The data from each dice is compared in an optical comparator with data from the ideal dice stored in a register.
摘要翻译：检测半导体晶片中的骰子上的缺陷的方法，其中扫描层中的每个骰子，并将来自每个骰子的数据与从预生产晶片上的相同电平获得的理想骰子收集的数据进行比较。来自每个骰子的数据在光学比较器中与来自存储在寄存器中的理想骰子的数据进行比较。

3. 发明授权

US06350639B1 Simplified graded LDD transistor using controlled polysilicon gate profile 有权
标题翻译：使用受控多晶硅栅极配置的简化分级LDD晶体管
公开(公告)号：US06350639B1
公开(公告)日：2002-02-26
申请号：US09832684
申请日：2001-04-10
申请人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
发明人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
IPC分类号： H01L218238
CPC分类号： H01L29/66598 , H01L21/266 , H01L21/28123 , H01L21/823814 , H01L29/665 , H01L29/6659
摘要： An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles.
摘要翻译：通过在半导体衬底上形成栅极氧化层制造具有LDD结构的超大规模CMOS集成电路半导体器件; 在所述栅极氧化物层上形成多晶硅层; 在所述多晶硅层上形成第一掩模层; 图案化和蚀刻第一掩模层以形成第一栅极掩模; 各向异性地蚀刻所述多晶硅层以形成第一多晶硅栅极，其中所述第一多晶硅栅极具有具有倾斜轮廓的侧壁，并且所述倾斜轮廓在所述LDD结构的离子注入期间用作掩模，以将所得到的LDD结构远离所述第二多晶硅的边缘随后将形成具有基本垂直轮廓的多晶硅栅极。

4. 发明授权

US6100593A Multiple chip hybrid package using bump technology 失效
标题翻译：多芯片混合封装采用凸点技术
公开(公告)号：US6100593A
公开(公告)日：2000-08-08
申请号：US32362
申请日：1998-02-27
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L21/60 , H01L23/055 , H01L23/13 , H01L25/065 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/81 , H01L23/055 , H01L23/13 , H01L25/0652 , H01L2224/16145 , H01L2224/16225 , H01L2224/81801 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/16195
摘要： A multiple chip hybrid package using bump technology having multiple chips electrically connected using a flip chip technology such as solder bump technology. Portion of at least one chip is electrically connected to electrical leads connecting terminals inside the package to pins outside the package.
摘要翻译：使用具有多个芯片的凸块技术的多芯片混合封装，使用诸如焊料凸块技术的倒装芯片技术进行电连接。至少一个芯片的部分电连接到将封装内的端子连接到封装外部的引脚的电引线。

5. 发明授权

US6025259A Dual damascene process using high selectivity boundary layers 失效
标题翻译：双镶嵌工艺采用高选择性边界层
公开(公告)号：US6025259A
公开(公告)日：2000-02-15
申请号：US109113
申请日：1998-07-02
申请人： Allen S. Yu , Paul J. Steffan , Thomas Charles Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas Charles Scholer
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76811 , H01L21/76813
摘要： A method of manufacturing a semiconductor device with multiple dual damascene structures that maintains the maximum density. A first dual damascene structure having a first via and a first trench is formed in a first interlayer dielectric and a first etch stop layer formed on the planarized surface of the first interlayer dielectric. Two layers of interlayer dielectric separated by a second etch stop layer is formed on the surface of the first etch stop layer. A third etch stop layer is formed on the upper layer of interlayer dielectric and a first photoresist layer formed on the third etch stop layer. The photoresist layer is etched having a dimension coinciding with a width dimension of the first via. The third etch stop layer is selectively etched and the first photoresist layer removed and replaced by a second photoresist layer. The second photoresist layer is etched having a dimension coinciding with a width dimension of the first trench. The two layers of interlayer dielectric and the first, second and third etch stop layers are etched to form a second dual damascene structure having a second via and a second trench having the same dimensions as the first dual damascene structure.
摘要翻译：一种制造具有保持最大密度的多个双镶嵌结构的半导体器件的方法。具有第一通孔和第一沟槽的第一双镶嵌结构形成在形成在第一层间电介质的平坦化表面上的第一层间电介质和第一蚀刻停止层中。在第一蚀刻停止层的表面上形成由第二蚀刻停止层分隔的两层层间电介质。第三蚀刻停止层形成在层间电介质的上层和形成在第三蚀刻停止层上的第一光致抗蚀剂层。蚀刻具有与第一通孔的宽度尺寸一致的尺寸的光致抗蚀剂层。选择性地蚀刻第三蚀刻停止层，并且移除第一光致抗蚀剂层并由第二光致抗蚀剂层代替。蚀刻第二光致抗蚀剂层，其尺寸与第一沟槽的宽度尺寸重合。蚀刻两层层间电介质和第一，第二和第三蚀刻停止层以形成具有第二通孔的第二双镶嵌结构和具有与第一双镶嵌结构相同尺寸的第二沟槽。

6. 发明授权

US6013570A LDD transistor using novel gate trim technique 失效
标题翻译： LDD晶体管采用新颖的栅极贴装技术
公开(公告)号：US6013570A
公开(公告)日：2000-01-11
申请号：US118389
申请日：1998-07-17
申请人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
发明人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28123 , H01L29/66659
摘要： An ultra-large scale MOS integrated circuit semiconductor device is processed after the formation of the gate oxide and polysilicon layer by forming a forming a first mask layer over the polysilicon layer followed by a second mask layer over the first mask layer. The first mask layer and the second mask layer are patterned to form first gate mask and second gate mask respectively. The polysilicon gate is then formed by anisotropically etching the polysilicon layer. The second gate mask is then removed. The polysilicon gate is then etched isotropically to reduce its width using the gate oxide layer and the patterned first gate mask as hard masks. The first gate mask is then used as a mask for dopant implantation to form source and drain extensions which are spaced away from the edges of the polysilicon gate. Thereafter, the first gate mask is removed and a spacer is formed dopant implantation to form deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the source and drain extension junctions and junctions, and the spacer is removed. Since the source and drain extension junctions are spaced away from the edges of the polysilicon gate, the displacement of the source/drain extension junctions into the channel is reduced. This results in a device with reduced parasitic capacitance.
摘要翻译：在形成栅极氧化物和多晶硅层之后，通过在多晶硅层上形成第一掩模层，然后在第一掩模层上形成第二掩模层，来处理超大规模MOS集成电路半导体器件。图案化第一掩模层和第二掩模层以分别形成第一栅极掩模和第二栅极掩模。然后通过各向异性蚀刻多晶硅层形成多晶硅栅极。然后删除第二个门屏蔽。然后使用栅极氧化物层和图案化的第一栅极掩模作为硬掩模，各向异性腐蚀多晶硅栅极以减小其宽度。然后将第一栅极掩模用作掺杂剂注入的掩模，以形成与多晶硅栅极的边缘间隔开的源极和漏极延伸部。此后，去除第一栅极掩模并且形成衬垫以形成掺杂剂注入以形成深的源极和漏极结。然后，较高温度的快速热退火优化源极和漏极延伸接合部和接合部，并且移除间隔物。由于源极和漏极延伸接头与多晶硅栅极的边缘间隔开，所以源极/漏极延伸接合部分到沟道的位移被减小。这导致具有降低的寄生电容的器件。

7. 发明授权

US06433371B1 Controlled gate length and gate profile semiconductor device 有权
标题翻译：控制栅极长度和栅极配置半导体器件
公开(公告)号：US06433371B1
公开(公告)日：2002-08-13
申请号：US09493428
申请日：2000-01-29
申请人： Thomas C. Scholer , Allen S. Yu , Paul J. Steffan
发明人： Thomas C. Scholer , Allen S. Yu , Paul J. Steffan
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/42376 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Ultra-large scale CMOS integrated circuit semiconductor devices are provided which have width- and profile-controlled, inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.
摘要翻译：提供了超大规模CMOS集成电路半导体器件，其具有具有LDD结构的宽度和轮廓控制的倒梯形门，其具有逐渐的掺杂分布并且用于接触。通过在衬底上形成阻挡层，在阻挡层上形成栅极层，在栅极层中形成反向梯形栅极沟槽，在衬底上的反向梯形栅极沟槽中沉积栅极电介质，形成衬底上的结构，从而形成在反向梯形栅极沟槽中的多晶硅栅极，去除栅极层和阻挡层以限定栅极间隔物，用掺杂剂将栅极间隔物周围注入基板以形成源极/漏极延伸结，以及制备源极/漏极延伸结和导电连接门。

8. 发明授权

US06430572B1 Recipe management database system 有权
标题翻译：食谱管理数据库系统
公开(公告)号：US06430572B1
公开(公告)日：2002-08-06
申请号：US09264362
申请日：1999-03-08
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06F1730
CPC分类号： G06F17/30289 , G06F17/30371 , Y10S707/99945 , Y10S707/99948
摘要： A scan tool recipe management database system for recipes utilized in the scanning of semiconductor wafers during the manufacture of the semiconductor wafers. The scan tool recipe management database system includes workstations at each scan tool for simultaneously inputting recipes and changes to the recipes to the scan tool and to a scan tool recipe database.
摘要翻译：一种扫描工具配方管理数据库系统，用于在制造半导体晶片期间在半导体晶片的扫描中使用的配方。扫描工具配方管理数据库系统包括每个扫描工具上的工作站，用于同时输入食谱和对扫描工具和扫描工具配方数据库的配方更改。

9. 发明授权

US06377898B1 Automatic defect classification comparator die selection system 失效
标题翻译：自动缺陷分类比较器模具选择系统
公开(公告)号：US06377898B1
公开(公告)日：2002-04-23
申请号：US09294246
申请日：1999-04-19
申请人： Paul J. Steffan , Allen S. Yu
发明人： Paul J. Steffan , Allen S. Yu
IPC分类号： G06F1900
CPC分类号： H01L22/20
摘要： A method of analyzing and classifying defects on semiconductor wafers during a semiconductor manufacturing process using a comparator die selector system wherein an automatic defect classification review tool compares defects on a die location with an identical location on an identical die. The automatic defect classification review tool locates identical die with information from the comparator die selector system.
摘要翻译：一种在使用比较模片选择系统的半导体制造过程中对半导体晶片上的缺陷进行分析和分类的方法，其中自动缺陷分类评估工具将模具位置上的缺陷与相同模具上的相同位置进行比较。自动缺陷分类检查工具与来自比较器管芯选择器系统的信息定位相同的管芯。

10. 发明授权

US06291252B1 Automatic method to eliminate first-wafer effect 有权
标题翻译：自动消除第一晶圆效应的方法
公开(公告)号：US06291252B1
公开(公告)日：2001-09-18
申请号：US09345175
申请日：1999-06-30
申请人： Allen S. Yu , Paul J. Steffan
发明人： Allen S. Yu , Paul J. Steffan
IPC分类号： H01L2100
CPC分类号： H01L21/67276 , Y10T29/41
摘要： A method of manufacturing semiconductor wafers in a processing tool in which it is determined whether the tool has been on idle beyond a predetermined period of time. If the tool has not been on idle beyond the predetermined period of time, a product wafer is automatically processed. If the tool has been on idle beyond the predetermined period of time, a conditioning wafer is automatically processed.
摘要翻译：一种在处理工具中制造半导体晶片的方法，其中确定工具是否已经在预定时间段之后空转。如果工具在预定时间之后没有闲置，则产品晶片被自动处理。如果工具在预定时间段之后已经空转，则调节晶片被自动处理。

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