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1. 发明授权

US06448606B1 Semiconductor with increased gate coupling coefficient 有权
标题翻译：半导体具有增加的栅极耦合系数
公开(公告)号：US06448606B1
公开(公告)日：2002-09-10
申请号：US09513261
申请日：2000-02-24
申请人： Allen S. Yu , Thomas C. Scholer , Paul J. Steffan
发明人： Allen S. Yu , Thomas C. Scholer , Paul J. Steffan
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A reduced device geometry semiconductor memory device is provided which has increased device efficiency because of an increased gate coupling coefficient. Shallow trench isolations are formed in a semiconductor substrate. The shallow trench isolations are selectively shaped in order to form a control gate dielectric layer later with a large width relative to the width between the floating gates.
摘要翻译：提供了一种缩小的器件几何形状半导体存储器件，其由于增加的栅极耦合系数而具有增加的器件效率。在半导体衬底中形成浅沟槽隔离。浅沟槽隔离件被选择成形以便稍后形成相对于浮动栅极之间宽度的大宽度的控制栅极电介质层。

2. 发明授权

US6100593A Multiple chip hybrid package using bump technology 失效
标题翻译：多芯片混合封装采用凸点技术
公开(公告)号：US6100593A
公开(公告)日：2000-08-08
申请号：US32362
申请日：1998-02-27
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L21/60 , H01L23/055 , H01L23/13 , H01L25/065 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/81 , H01L23/055 , H01L23/13 , H01L25/0652 , H01L2224/16145 , H01L2224/16225 , H01L2224/81801 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/16195
摘要： A multiple chip hybrid package using bump technology having multiple chips electrically connected using a flip chip technology such as solder bump technology. Portion of at least one chip is electrically connected to electrical leads connecting terminals inside the package to pins outside the package.
摘要翻译：使用具有多个芯片的凸块技术的多芯片混合封装，使用诸如焊料凸块技术的倒装芯片技术进行电连接。至少一个芯片的部分电连接到将封装内的端子连接到封装外部的引脚的电引线。

3. 发明授权

US6133140A Method of manufacturing dual damascene utilizing anisotropic and isotropic properties 有权
标题翻译：使用各向异性特性制造双镶嵌的方法
公开(公告)号：US6133140A
公开(公告)日：2000-10-17
申请号：US165782
申请日：1998-10-02
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76807
摘要： A method of manufacturing a semiconductor device with dual damascene structures. A first and second layer of interlayer dielectric separated by a first layer of etch stop material is formed on the surface of a semiconductor substrate on and in which active devices have been formed. A second layer of an etch stop material is formed on the surface of the second layer of interlayer dielectric. A layer of photoresist is formed on the second layer of etch stop material and is patterned and etched to expose portions of the second etch stop material. The exposed portions of the second etch stop material are anisotropically etched exposing portions of the second layer of interlayer dielectric. The exposed portions of the second layer of interlayer dielectric are first anisotropically etched and then isotropically etched. The etch stop layer between the first and second interlayer dielectric is anisotropically etched and the first layer of interlayer dielectric is anisotropically etched. The etched portions are then filled with a conductive material.
摘要翻译：一种制造具有双镶嵌结构的半导体器件的方法。在半导体衬底的表面上形成由第一层蚀刻停止材料隔开的第一和第二层间介质层，其中形成了有源器件。第二层蚀刻停止材料形成在第二层间电介质层的表面上。在第二层蚀刻停止材料上形成一层光致抗蚀剂，并对其进行图案化和蚀刻以暴露第二蚀刻停止材料的部分。第二蚀刻停止材料的暴露部分被各向异性蚀刻，暴露第二层间电介质层的部分。首先对第二层间介电层的暴露部分进行各向异性蚀刻，然后进行各向同性蚀刻。在第一和第二层间电介质之间的蚀刻停止层被各向异性蚀刻，并且第一层间介电层被各向异性地蚀刻。然后用导电材料填充蚀刻部分。

4. 发明授权

US6103616A Method to manufacture dual damascene structures by utilizing short resist spacers 有权
标题翻译：通过利用短抗蚀剂间隔物制造双镶嵌结构的方法
公开(公告)号：US6103616A
公开(公告)日：2000-08-15
申请号：US136867
申请日：1998-08-19
申请人： Allen S. Yu , Thomas C. Scholer , Paul J. Steffan
发明人： Allen S. Yu , Thomas C. Scholer , Paul J. Steffan
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76811 , H01L21/76813
摘要： A method of manufacturing semiconductor devices wherein a partially completed semiconductor device having a first and second layer of interlayer dielectric and a first and second etch stop layer has the second etch stop layer masked and etched with an etch pattern having dimensions of the trench structure to be formed in the second interlayer dielectric. The second layer dielectric and first etch stop layer are then masked and etched with an etch pattern having dimensions of the via structure to be formed in the first interlayer dielectric. The remaining portions of the photoresist is removed and exposed portions of the second layer of interlayer dielectric and the first layer of interlayer dielectric are then etched simultaneously. The via structure and trench structure are then simultaneously filled with a conductive material.
摘要翻译：一种制造半导体器件的方法，其中具有第一和第二层间电介质层和第一和第二蚀刻停止层的部分完成的半导体器件具有用具有沟槽结构尺寸的蚀刻图案被掩蔽和蚀刻的第二蚀刻停止层形成在第二层间电介质中。然后用具有要形成在第一层间电介质中的通孔结构的尺寸的蚀刻图案掩蔽和蚀刻第二层电介质和第一蚀刻停止层。去除光致抗蚀剂的剩余部分，然后同时蚀刻第二层层间电介质层和第一层间电介质层的暴露部分。然后通孔结构和沟槽结构同时填充导电材料。

5. 发明授权

US06433371B1 Controlled gate length and gate profile semiconductor device 有权
标题翻译：控制栅极长度和栅极配置半导体器件
公开(公告)号：US06433371B1
公开(公告)日：2002-08-13
申请号：US09493428
申请日：2000-01-29
申请人： Thomas C. Scholer , Allen S. Yu , Paul J. Steffan
发明人： Thomas C. Scholer , Allen S. Yu , Paul J. Steffan
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/42376 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Ultra-large scale CMOS integrated circuit semiconductor devices are provided which have width- and profile-controlled, inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.
摘要翻译：提供了超大规模CMOS集成电路半导体器件，其具有具有LDD结构的宽度和轮廓控制的倒梯形门，其具有逐渐的掺杂分布并且用于接触。通过在衬底上形成阻挡层，在阻挡层上形成栅极层，在栅极层中形成反向梯形栅极沟槽，在衬底上的反向梯形栅极沟槽中沉积栅极电介质，形成衬底上的结构，从而形成在反向梯形栅极沟槽中的多晶硅栅极，去除栅极层和阻挡层以限定栅极间隔物，用掺杂剂将栅极间隔物周围注入基板以形成源极/漏极延伸结，以及制备源极/漏极延伸结和导电连接门。

6. 发明授权

US06239008B1 Method of making a density multiplier for semiconductor device manufacturing 有权
标题翻译：制造用于半导体器件制造的密度倍增器的方法
公开(公告)号：US06239008B1
公开(公告)日：2001-05-29
申请号：US09407907
申请日：1999-09-29
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L213205
CPC分类号： H01L21/3081 , H01L21/0274 , H01L21/0277 , H01L21/0278 , H01L21/0332
摘要： A method of manufacturing a semiconductor device with increased density of structures that have at least one dimension less than that provided by the lithography system being used in the manufacturing process.
摘要翻译：制造具有比制造工艺中使用的光刻系统所提供的尺寸小至少一个尺寸的结构密度增加的半导体器件的方法。

7. 发明授权

US5985753A Method to manufacture dual damascene using a phantom implant mask 有权
标题翻译：使用幻影植入物掩模制造双镶嵌的方法
公开(公告)号：US5985753A
公开(公告)日：1999-11-16
申请号：US136866
申请日：1998-08-19
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L21/033 , H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76825 , H01L21/0337 , H01L21/31144 , H01L21/7681 , H01L21/76813 , H01L2221/1026
摘要： Methods of manufacturing semiconductor devices wherein a selected layer is implanted with heavy ions in a pattern having dimensions of a via structure to be formed in a first layer of interlayer dielectric. In a first embodiment, the ions are implanted in an etch stop layer formed between a first and second layer of interlayer dielectric. In a second embodiment, the ions are implanted in the second layer of interlayer dielectric. Selective etch processes form a trench structure in the second layer of interlayer dielectric and form a via structure in the first layer of interlayer dielectric. The via structure and trench structure are filled with a conductive material.
摘要翻译：制造半导体器件的方法，其中所选择的层以具有要形成在第一层间电介质层中的通孔结构的尺寸的图案中注入重离子。在第一实施例中，将离子注入形成在第一和第二层间电介质层之间的蚀刻停止层中。在第二实施例中，将离子注入第二层间电介质层。选择性蚀刻工艺在第二层间电介质层中形成沟槽结构，并在第一层间电介质层中形成通孔结构。通孔结构和沟槽结构填充有导电材料。

8. 发明授权

US06524916B1 Controlled gate length and gate profile semiconductor device and manufacturing method therefor 有权
标题翻译：控制栅极长度和栅极配置半导体器件及其制造方法
公开(公告)号：US06524916B1
公开(公告)日：2003-02-25
申请号：US10137568
申请日：2002-05-01
申请人： Thomas C. Scholer , Allen S. Yu , Paul J. Steffan
发明人： Thomas C. Scholer , Allen S. Yu , Paul J. Steffan
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/42376 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An ultra-large scale integrated circuit semiconductor device is provided which has inverted trapezoidal gates with LDD structures having gradual doping profiles and salicided for contacts. The structures are manufactured on a substrate by forming a barrier layer over the substrate, forming a gate layer over the barrier layer, forming inverted trapezoidal gate trenches into the gate layer that are a function of the thickness of the gate layer, depositing a gate dielectric in the inverted trapezoidal gate trenches on the substrate, forming polysilicon gates in the inverted trapezoidal gate trenches, removing the gate layer and the barrier layer to define gate spacers, implanting the substrate around the gate spacers with a dopant to form source/drain extension junctions, and preparing the source/drain extension junctions and the gates for conductive connections.
摘要翻译：提供了一种超大规模集成电路半导体器件，其具有具有逐渐掺杂分布的LDD结构的倒梯形栅极并且用于接触。通过在衬底上形成阻挡层，在阻挡层上形成栅极层，在栅极层中形成倒梯形栅极沟槽，栅极层的厚度为栅极层的厚度，沉积栅极电介质在衬底上的倒梯形栅极沟槽中，在反向梯形栅极沟槽中形成多晶硅栅极，去除栅极层和势垒层以限定栅极间隔物，用掺杂剂将栅极间隔物周围注入基板以形成源极/漏极延伸结并且准备用于导电连接的源极/漏极延伸结和栅极。

9. 发明授权

US06287968B1 Method of defining copper seed layer for selective electroless plating processing 有权
标题翻译：定义用于选择性化学镀处理的铜籽晶层的方法
公开(公告)号：US06287968B1
公开(公告)日：2001-09-11
申请号：US09225175
申请日：1999-01-04
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76865 , H01L21/76871 , H01L21/76874 , H01L21/76879
摘要： A method of manufacturing semiconductor wafers using electroless plating processing. A partially completed semiconductor wafer having trenches and vias formed in a layer of interlayer dielectric has a barrier layer globally formed on the surface of the partially completed semiconductor wafer. A seed layer is globally formed on the surface of the barrier layer. The barrier and seed layers are removed from portions of the surface of the partially completed semiconductor wafer on which plating is not to occur. The partially completed semiconductor wafer is then subjected to an electroless plating process and conductive material is plated on those portions of the seed layer that remains on the partially completed semiconductor wafer.
摘要翻译：使用化学镀处理制造半导体晶片的方法。在层间电介质层中形成的具有沟槽和通孔的部分完成的半导体晶片具有全部形成在部分完成的半导体晶片的表面上的势垒层。种子层全局地形成在阻挡层的表面上。从不发生电镀的部分完成的半导体晶片的表面的部分去除阻挡层和种子层。然后对部分完成的半导体晶片进行化学镀处理，并且将导电材料电镀在保留在部分完成的半导体晶片上的籽晶层的那些部分上。

10. 发明授权

US6107204A Method to manufacture multiple damascene by utilizing etch selectivity 有权
标题翻译：通过利用蚀刻选择性制造多镶嵌的方法
公开(公告)号：US6107204A
公开(公告)日：2000-08-22
申请号：US165783
申请日：1998-10-02
申请人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
发明人： Allen S. Yu , Paul J. Steffan , Thomas C. Scholer
IPC分类号： H01L21/311 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768
CPC分类号： H01L21/76807 , H01L21/31116 , H01L21/3145 , H01L21/31612 , H01L21/3185
摘要： A method of manufacturing a semiconductor device having multiple layers of interconnects that are filled in a single conductive material filling step. Two layers of interlayer dielectric separated by an etch stop layer are formed over a layer including metal structures in contact with electrodes of active devices formed in and on a semiconductor substrate. A layer of photoresist is formed on a second etch stop layer formed on the upper layer of interlayer dielectric. The layer of photoresist is patterned and etched. Masking and etching processes form openings in the first and second layers of interlayer dielectric including openings to the metal structures. The openings are filled in a single conductive material filling step.
摘要翻译：一种制造具有填充在单个导电材料填充步骤中的多层互连的半导体器件的方法。在包括与在半导体衬底中形成的有源器件的电极接触的金属结构的层上形成由蚀刻停止层分隔的两层层间电介质。在形成在层间电介质的上层上的第二蚀刻停止层上形成一层光致抗蚀剂。对光致抗蚀剂层进行图案化和蚀刻。掩模和蚀刻工艺在第一层和第二层的层间电介质中形成开口，其包括到金属结构的开口。开口填充在单个导电材料填充步骤中。

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