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1. 发明授权

US09412883B2 Methods and apparatus for MOS capacitors in replacement gate process 有权
标题翻译：替代栅极工艺中MOS电容器的方法和装置
公开(公告)号：US09412883B2
公开(公告)日：2016-08-09
申请号：US13303083
申请日：2011-11-22
申请人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
发明人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
IPC分类号： H01L29/94 , H01L27/06 , H01L27/08 , H01L49/02
CPC分类号： H01L21/822 , H01L27/0629 , H01L27/0811 , H01L28/20 , H01L29/401 , H01L29/94
摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.
摘要翻译：替代栅极工艺中多晶硅MOS电容器的方法和装置。一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。公开了通过该方法制造的装置。

2. 发明申请

US20130126953A1 Methods and Apparatus for MOS Capacitors in Replacement Gate Process 有权
标题翻译：替代栅极工艺中MOS电容器的方法与装置
公开(公告)号：US20130126953A1
公开(公告)日：2013-05-23
申请号：US13303083
申请日：2011-11-22
申请人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
发明人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L21/822 , H01L27/0629 , H01L27/0811 , H01L28/20 , H01L29/401 , H01L29/94
摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.
摘要翻译：替代栅极工艺中多晶硅MOS电容器的方法和装置。一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。公开了通过该方法制造的装置。

3. 发明授权

US09287252B2 Semiconductor mismatch reduction 有权
标题翻译：半导体失配减少
公开(公告)号：US09287252B2
公开(公告)日：2016-03-15
申请号：US13048411
申请日：2011-03-15
申请人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
发明人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
IPC分类号： H01L29/12 , H01L27/02
CPC分类号： H01L27/0207
摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
摘要翻译：公开了一种用于减小密度失配的系统和方法。一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

4. 发明授权

US08803320B2 Integrated circuits and fabrication methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08803320B2
公开(公告)日：2014-08-12
申请号：US13025763
申请日：2011-02-11
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H01L29/40
CPC分类号： H01L23/552 , H01L23/5225 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a signal line routed in a first direction. A first shielding pattern is disposed substantially parallel with the signal line. The first shielding pattern has a first edge having a first dimension and a second edge having a second dimension. The first edge is substantially parallel with the signal line. The first dimension is larger than the second dimension. A second shielding pattern is disposed substantially parallel with the signal line. The second shielding pattern has a third edge having a third dimension and a fourth edge having a fourth dimension. The third edge is substantially parallel with the signal line. The third dimension is larger than the fourth dimension. The fourth edge faces the second edge. A first space is between the second and fourth edges.
摘要翻译：集成电路包括沿第一方向布线的信号线。第一屏蔽图案基本上与信号线平行设置。第一屏蔽图案具有具有第一尺寸的第一边缘和具有第二尺寸的第二边缘。第一边缘基本上与信号线平行。第一个维度大于第二个维度。第二屏蔽图案基本上与信号线平行设置。第二屏蔽图案具有具有第三尺寸的第三边缘和具有第四尺寸的第四边缘。第三边缘基本上与信号线平行。第三维度大于第四维度。第四个边缘面向第二个边缘。第一空间在第二和第四边之间。

5. 发明申请

US20140008817A1 THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT 审中-公开
标题翻译：通过硅（TSV）隔离结构减少3D集成电路中的噪声
公开(公告)号：US20140008817A1
公开(公告)日：2014-01-09
申请号：US14024925
申请日：2013-09-12
申请人： Jaw-Juinn HORNG , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
发明人： Jaw-Juinn HORNG , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
摘要翻译：提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能通过半导体衬底传播的电噪声。隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

6. 发明申请

US20130346935A1 SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION 有权
公开(公告)号：US20130346935A1
公开(公告)日：2013-12-26
申请号：US14012142
申请日：2013-08-28
申请人： Young-Chow PENG , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
发明人： Young-Chow PENG , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.

7. 发明授权

US07973552B2 On-die terminators formed of coarse and fine resistors 有权
标题翻译：由粗细和电阻器形成的裸片终端
公开(公告)号：US07973552B2
公开(公告)日：2011-07-05
申请号：US11950419
申请日：2007-12-04
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H01L27/0802 , H01L28/20
摘要： An integrated circuit includes a semiconductor substrate; a first node; a second node; and a first plurality of resistors, each in a first plurality of resistor units. Each of the first plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The integrated circuit further includes a second plurality of resistors, each in a second plurality of resistor units. Each of the second plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The first plurality of resistors is formed of a first material. The second plurality of resistors is formed of a second material different from the first material. The integrated circuit further includes a switch in one of the first and the second plurality of resistor units and serially connected to a resistor.
摘要翻译：集成电路包括半导体衬底; 第一个节点; 第二个节点; 以及第一多个电阻器，每个在第一多个电阻器单元中。第一多个电阻器单元中的每一个包括连接到第一节点的第一端和连接到第二节点的第二端。集成电路还包括第二多个电阻器，每个电阻器在第二多个电阻器单元中。第二多个电阻器单元中的每一个包括连接到第一节点的第一端和连接到第二节点的第二端。第一多个电阻器由第一材料形成。第二多个电阻器由不同于第一材料的第二材料形成。集成电路还包括在第一和第二多个电阻器单元之一中的开关，并且串联连接到电阻器。

8. 发明授权

US07692442B2 Apparatus for detecting a current and temperature for an integrated circuit 有权
标题翻译：用于检测集成电路的电流和温度的装置
公开(公告)号：US07692442B2
公开(公告)日：2010-04-06
申请号：US11281142
申请日：2005-11-17
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： G01R31/26
CPC分类号： G01R31/025 , G01K7/015 , G01R19/0092 , G01R31/2621 , G01R31/2628
摘要： The present invention discloses an apparatus for detecting a current flowing from a first node to a second node. One or more MOS devices are serially coupled between the first and second nodes. Each of the MOS devices has its body connected to its source and its gate connected to its drain for providing each MOS device with a voltage difference between its gate and its source that is lower than a threshold voltage of the same, such that a voltage difference measured between the first and second nodes responds to a change of the current exponentially.
摘要翻译：本发明公开了一种用于检测从第一节点流向第二节点的电流的装置。一个或多个MOS器件串联耦合在第一和第二节点之间。每个MOS器件的主体连接到其源极，并且其栅极连接到其漏极，以为每个MOS器件提供其栅极和源极之间的电压差低于其栅极电压，使得电压差在第一和第二节点之间测量响应于当前指数变化。

9. 发明授权

US07501884B2 Capacitive circuit employing low voltage MOSFETs and method of manufacturing same 有权
标题翻译：采用低压MOSFET的电容电路及其制造方法
公开(公告)号：US07501884B2
公开(公告)日：2009-03-10
申请号：US10866155
申请日：2004-06-11
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： G01F1/10 , G01F3/00
CPC分类号： H01L27/0811 , H01L27/0629 , H03H7/25
摘要： Disclosed herein are a capacitive circuit for use on a semiconductor substrate, and related method of manufacturing the same. In one aspect, the capacitive circuit includes a plurality of MOSFETs each having their respective source and drain electrically coupled together, where the plurality of MOSFETs are series-coupled to each other by electrically coupling a gate of one of the plurality to the coupled source/drain of another of the plurality. In this embodiment, the circuit also includes a power supply electrically coupled to the plurality of MOSFETs, where a coupled source/drain of one of the plurality of MOSFETs at a first end of the series is electrically coupled to a first terminal of the power supply, and a gate of another of the plurality of MOSFETs at a second end of the series is electrically coupled to a second terminal of the power supply. The circuit also includes a plurality of resistive elements each electrically parallel-coupled across corresponding ones of the plurality of MOSFETs.
摘要翻译：这里公开了用于半导体衬底的电容电路及其制造方法。在一个方面中，电容电路包括多个MOSFET，它们各自具有电耦合在一起的源极和漏极，其中通过将多个MOSFET中的一个的栅极电耦合到耦合的源极/漏极的多个MOSFET彼此串联耦合，多余的另一个的排水。在该实施例中，电路还包括电耦合到多个MOSFET的电源，其中在该串联的第一端的多个MOSFET中的一个MOSFET的耦合源极/漏极电耦合到电源的第一端子并且在该串联的第二端的多个MOSFET中另一个的栅极电耦合到电源的第二端子。电路还包括多个电阻元件，每个电阻元件电平行耦合在多个MOSFET中的相应的MOSFET上。

10. 外观设计

USD537065S1 Telephone 有权
公开(公告)号：USD537065S1
公开(公告)日：2007-02-20
申请号：US29236085
申请日：2005-09-16
申请人： Chung-Hui Chen
设计人： Chung-Hui Chen

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