专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09612606B2 Bandgap reference circuit 有权
公开(公告)号：US09612606B2
公开(公告)日：2017-04-04
申请号：US13472063
申请日：2012-05-15
申请人： Jaw-Juinn Horng , Kuo-Feng Yu , Chung-Hui Chen
发明人： Jaw-Juinn Horng , Kuo-Feng Yu , Chung-Hui Chen
IPC分类号： G05F3/30
CPC分类号： G05F3/16 , G05F3/30
摘要： A bandgap reference circuit including two sets of bipolar junction transistors (BJTs). A first set of two or more BJTs configured to electrically connect in a parallel arrangement. The first set of BJTs is configured to produce a first proportional to absolute temperature (PTAT) signal. A second set of two or more BJTs configured to electrically connect in a parallel arrangement. The second set of BJTs is configured to produce a second PTAT signal. A circuitry configured to electrically connect to the first set of BJTs and the second set of BJTs. The circuitry is configured to combine the first PTAT signal and the second PTAT signal to produce a reference voltage.

2. 发明授权

US09412883B2 Methods and apparatus for MOS capacitors in replacement gate process 有权
标题翻译：替代栅极工艺中MOS电容器的方法和装置
公开(公告)号：US09412883B2
公开(公告)日：2016-08-09
申请号：US13303083
申请日：2011-11-22
申请人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
发明人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
IPC分类号： H01L29/94 , H01L27/06 , H01L27/08 , H01L49/02
CPC分类号： H01L21/822 , H01L27/0629 , H01L27/0811 , H01L28/20 , H01L29/401 , H01L29/94
摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.
摘要翻译：替代栅极工艺中多晶硅MOS电容器的方法和装置。一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。公开了通过该方法制造的装置。

3. 发明授权

US09196540B2 FinFET structure with novel edge fins 有权
标题翻译： FinFET结构具有新颖的边缘鳍片
公开(公告)号：US09196540B2
公开(公告)日：2015-11-24
申请号：US13368027
申请日：2012-02-07
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H01L27/108 , H01L21/8234 , H01L21/84 , H01L29/66 , H01L27/088 , H01L27/12
CPC分类号： H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/6681
摘要： A semiconductor device including field-effect transistors (finFETs) formed on a silicon substrate. The device includes a number of active areas each having a number of equally-spaced fins separated into regular fins and at least one edge fin, a gate structure over the regular fins, and a drain region as well as a source region electrically connected to the regular fins and disconnected to the at least one edge fin. The edge fins may be floating, connected to a potential source, or serve as a part of a decoupling capacitor.
摘要翻译：一种半导体器件，包括形成在硅衬底上的场效晶体管（finFET）。该装置包括多个有效区域，每个有效区域具有分开成规则翅片和至少一个边缘翅片的数个等间隔的翅片，规则散热片上的栅极结构以及漏极区域以及与该区域电连接的源极区域规则散热片并与至少一个边缘鳍片断开。边缘鳍片可以浮动，连接到电位源，或者用作去耦电容器的一部分。

4. 发明授权

US08847320B2 Decoupling capacitor and layout for the capacitor 有权
标题翻译：去耦电容器和电容布局
公开(公告)号：US08847320B2
公开(公告)日：2014-09-30
申请号：US13362411
申请日：2012-01-31
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H01L23/02 , H01L21/70 , H01L27/06 , H01L21/8222
CPC分类号： H01L27/0629 , H01L27/0207 , H01L27/0811 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.
摘要翻译：一种器件包括具有第一掺杂剂类型的第一和第二注入区的半导体衬底。栅极绝缘层和栅电极设置在第一和第二植入区域之间的电阻器区域的上方。第一介电层位于第一注入区上。提供一种接触结构，包括与门电极导电接触的第一接触部分，第一接触部分的至少一部分直接在栅电极上。第二接触部分直接接触第一接触部分并直接形成在第一介电层上。第三接触部分形成在第二植入区域上。

5. 发明授权

US08610241B1 Homo-junction diode structures using fin field effect transistor processing 有权
标题翻译：使用鳍式场效应晶体管处理的同相二极管结构
公开(公告)号：US08610241B1
公开(公告)日：2013-12-17
申请号：US13494795
申请日：2012-06-12
申请人： Chia-Hsin Hu , Sun-Jay Chang , Jaw-Juinn Horng , Chung-Hui Chen
发明人： Chia-Hsin Hu , Sun-Jay Chang , Jaw-Juinn Horng , Chung-Hui Chen
IPC分类号： H01L21/70
CPC分类号： H01L27/0623 , H01L27/0629 , H01L27/0635 , H01L27/0664 , H01L27/0814 , H01L29/861
摘要： Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.
摘要翻译：通过在FinFET形成过程中利用各种工艺步骤，在包括鳍状场效应晶体管（FinFET）的IC器件中形成二极管和双极结型晶体管（BJT）。二极管或BJT包括具有不同深度的n阱的隔离散热片区域和散热片阵列区域，以及围绕隔离鳍片区域中的n阱的散热片阵列区域的一部分中的p阱。二极管和BJT的n阱和p阱与FinFET n阱和p阱一起植入。

6. 发明授权

US08549453B2 Semiconductor device feature density gradient verification 有权
标题翻译：半导体器件特征密度梯度校验
公开(公告)号：US08549453B2
公开(公告)日：2013-10-01
申请号：US13362914
申请日：2012-01-31
申请人： Young-Chow Peng , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
发明人： Young-Chow Peng , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.
摘要翻译：提供了一种用于验证半导体器件布局中存在可接受的器件特征梯度和器件特征差异的方法。该方法提供了将设备布局划分成多个窗口并且测量或以其他方式确定每个窗口内的设备特征密度。设备布局包括各种设备区域，并且该方法提供了将一个区域内的平均设备特征密度与周围区域或其他区域进行比较，并且还用于确定设备特征密度的梯度。可以从特定设备区域到周围区域监视梯度。用于执行该方法的指令可以存储在计算机可读存储介质上并由处理器执行。

7. 发明申请

US20130200449A1 FINFET STRUCTURE WITH NOVEL EDGE FINS 有权
标题翻译： FINFET结构与新的边缘FINS
公开(公告)号：US20130200449A1
公开(公告)日：2013-08-08
申请号：US13368027
申请日：2012-02-07
申请人： Chung-Hui CHEN
发明人： Chung-Hui CHEN
IPC分类号： H01L27/06 , H01L21/336
CPC分类号： H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/6681
摘要： A semiconductor device including field-effect transistors (finFETs) formed on a silicon substrate. The device includes a number of active areas each having a number of equally-spaced fins separated into regular fins and at least one edge fin, a gate structure over the regular fins, and a drain region as well as a source region electrically connected to the regular fins and disconnected to the at least one edge fin. The edge fins may be floating, connected to a potential source, or serve as a part of a decoupling capacitor.
摘要翻译：一种半导体器件，包括形成在硅衬底上的场效晶体管（finFET）。该装置包括多个有效区域，每个有效区域具有分开成规则翅片和至少一个边缘翅片的数个等间隔的翅片，规则散热片上的栅极结构以及漏极区域以及与该区域电连接的源极区域规则散热片并与至少一个边缘鳍片断开。边缘鳍片可以浮动，连接到电位源，或者用作去耦电容器的一部分。

8. 发明申请

US20130147057A1 THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT 有权
标题翻译：通过硅（TSV）隔离结构减少3D集成电路中的噪声
公开(公告)号：US20130147057A1
公开(公告)日：2013-06-13
申请号：US13324405
申请日：2011-12-13
申请人： Jaw-Juinn HORNG , Chia-Lin YU , Chung-Hui CHEN , Der-Chyang YEH , Yung-Chow PENG
发明人： Jaw-Juinn HORNG , Chia-Lin YU , Chung-Hui CHEN , Der-Chyang YEH , Yung-Chow PENG
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
摘要翻译：提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能传播通过半导体衬底的电噪声。隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

9. 发明申请

US20130126953A1 Methods and Apparatus for MOS Capacitors in Replacement Gate Process 有权
标题翻译：替代栅极工艺中MOS电容器的方法与装置
公开(公告)号：US20130126953A1
公开(公告)日：2013-05-23
申请号：US13303083
申请日：2011-11-22
申请人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
发明人： Pai-Chieh Wang , Tung-Heng Hsieh , Yimin Huang , Chung-Hui Chen
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L21/822 , H01L27/0629 , H01L27/0811 , H01L28/20 , H01L29/401 , H01L29/94
摘要： Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.
摘要翻译：替代栅极工艺中多晶硅MOS电容器的方法和装置。一种方法包括在半导体衬底上设置栅极电介质层; 在所述电介质层上设置多晶硅栅极层; 图案化栅介电层和多晶硅栅极层以形成由至少最小多晶硅与多晶硅间距隔开的多个多晶硅门; 限定包含至少一个所述多晶硅栅极并且不包含形成伪栅极的所述多晶硅栅极中的至少一个的多晶硅电阻器区域; 在层间电介质层上沉积掩模层; 图案化掩模层以暴露伪栅极; 去除虚拟栅极下面的伪栅极和栅极电介质层，以将沟槽留在层间电介质层中; 以及在层间电介质层的沟槽中形成高k金属栅极器件。公开了通过该方法制造的装置。

10. 发明申请

US20120235208A1 Semiconductor Mismatch Reduction 有权
标题翻译：半导体失配减少
公开(公告)号：US20120235208A1
公开(公告)日：2012-09-20
申请号：US13048411
申请日：2011-03-15
申请人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
发明人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
IPC分类号： H01L29/12 , H01L21/66
CPC分类号： H01L27/0207
摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
摘要翻译：公开了一种用于减小密度失配的系统和方法。一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式