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1. 发明申请

US20130147057A1 THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT 有权
标题翻译：通过硅（TSV）隔离结构减少3D集成电路中的噪声
公开(公告)号：US20130147057A1
公开(公告)日：2013-06-13
申请号：US13324405
申请日：2011-12-13
申请人： Jaw-Juinn HORNG , Chia-Lin YU , Chung-Hui CHEN , Der-Chyang YEH , Yung-Chow PENG
发明人： Jaw-Juinn HORNG , Chia-Lin YU , Chung-Hui CHEN , Der-Chyang YEH , Yung-Chow PENG
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
摘要翻译：提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能传播通过半导体衬底的电噪声。隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

2. 发明申请

US20140008817A1 THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT 审中-公开
标题翻译：通过硅（TSV）隔离结构减少3D集成电路中的噪声
公开(公告)号：US20140008817A1
公开(公告)日：2014-01-09
申请号：US14024925
申请日：2013-09-12
申请人： Jaw-Juinn HORNG , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
发明人： Jaw-Juinn HORNG , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
摘要翻译：提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能通过半导体衬底传播的电噪声。隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

3. 发明申请

US20130043541A1 LOW POWER/HIGH SPEED TSV INTERFACE DESIGN 有权
标题翻译：低功率/高速TSV接口设计
公开(公告)号：US20130043541A1
公开(公告)日：2013-02-21
申请号：US13546024
申请日：2012-07-11
申请人： Chung-Hui CHEN , Jaw-Juinn HORNG , Shuo-Mao CHEN , Der-Chyang YEH
发明人： Chung-Hui CHEN , Jaw-Juinn HORNG , Shuo-Mao CHEN , Der-Chyang YEH
IPC分类号： H01L23/48 , H01L29/78
CPC分类号： H01L25/0657 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L2225/06572 , H01L2924/0002 , H01L2924/00
摘要： A TSV interface circuit for a TSV provided in an interposer substrate that forms a connection between a first die and a second die includes a driving circuit provided in the first die and a receiver circuit provided in the second die where the driving circuit is coupled to a first supply voltage and a second supply voltage that are both lower than the interposer substrate voltage that substantially reduces the parasitic capacitance of the TSV. The receiver circuit is also coupled to the first supply voltage and the second supply voltage that are both lower than the interposer substrate voltage.
摘要翻译：设置在形成第一管芯和第二管芯之间的连接的插入器基板中的TSV的TSV接口电路包括设置在第一管芯中的驱动电路和设置在第二管芯中的接收器电路，其中驱动电路耦合到第一电源电压和第二电源电压均低于基本上降低TSV的寄生电容的插入器基板电压。接收器电路还耦合到低于插入器基板电压的第一电源电压和第二电源电压。

4. 发明申请

US20140042585A1 SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM 有权
标题翻译：用于设计半导体器件的系统，器件制造和使用该系统的方法
公开(公告)号：US20140042585A1
公开(公告)日：2014-02-13
申请号：US13569717
申请日：2012-08-08
申请人： Yung-Chow PENG , Wen-Shen CHOU , Jaw-Juinn HORNG
发明人： Yung-Chow PENG , Wen-Shen CHOU , Jaw-Juinn HORNG
IPC分类号： G06F17/50 , H01L27/00
CPC分类号： H01L27/0207 , G06F17/5072 , G06F17/5081
摘要： This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.
摘要翻译：本公开涉及制造半导体器件的方法。该方法包括将半导体器件的示意图设计与半导体器件的布局设计进行比较。该方法还包括基于布局设计生成布局样式信息，并基于布局设计和原理图设计生成阵列边缘信息。该方法还包括使用布局样式信息和阵列边缘信息来选择性地修改使用智能虚拟插入的布局设计。该方法还包括使用布局样式信息和阵列边缘信息对修改的布局设计执行设计规则检查。本公开还涉及一种用于制造半导体器件和半导体器件的系统。

5. 发明申请

US20130328614A1 DEVICE LAYOUT FOR REFERENCE AND SENSOR CIRCUITS 有权
标题翻译：参考和传感器电路的器件布局
公开(公告)号：US20130328614A1
公开(公告)日：2013-12-12
申请号：US13494060
申请日：2012-06-12
申请人： Jaw-Juinn HORNG , Chung-Hui CHEN , Sun-Jay CHANG , Chia-Hsin HU
发明人： Jaw-Juinn HORNG , Chung-Hui CHEN , Sun-Jay CHANG , Chia-Hsin HU
IPC分类号： H01L27/16 , H01L27/082
CPC分类号： H01L27/0814 , H01L27/0207
摘要： A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.
摘要翻译：带隙参考电路包括耦合在第一电源节点和一对中间电压节点之间的基于误差放大器的电流镜，以及用于提供比例绝对温度（PTAT）电流的匹配二极管对。匹配二极管对包括连接在来自一对中间电压节点的第一中间电压节点和第二电源节点之间的第一二极管，以及与来自所述一对中间电压的第二中间电压节点之间的电阻器串联连接的第二二极管节点和第二个供应节点。每个二极管具有一个同相结合的P-N二极管结。

6. 发明申请

US20130328162A1 HOMO-JUNCTION DIODE STRUCTURES USING FIN FIELD EFFECT TRANSISTOR PROCESSING 有权
标题翻译：使用熔点效应晶体管加工的HOMO-JUNCTION DIODE结构
公开(公告)号：US20130328162A1
公开(公告)日：2013-12-12
申请号：US13494795
申请日：2012-06-12
申请人： Chia-Hsin HU , Sun-Jay CHANG , Jaw-Juinn HORNG , Chung-Hui CHEN
发明人： Chia-Hsin HU , Sun-Jay CHANG , Jaw-Juinn HORNG , Chung-Hui CHEN
IPC分类号： H01L29/73 , H01L21/331 , H01L21/762
CPC分类号： H01L27/0623 , H01L27/0629 , H01L27/0635 , H01L27/0664 , H01L27/0814 , H01L29/861
摘要： Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.
摘要翻译：通过在FinFET形成过程中利用各种工艺步骤，在包括鳍状场效应晶体管（FinFET）的IC器件中形成二极管和双极结型晶体管（BJT）。二极管或BJT包括具有不同深度的n阱的隔离散热片区域和散热片阵列区域，以及围绕隔离鳍片区域中的n阱的散热片阵列区域的一部分中的p阱。二极管和BJT的n阱和p阱与FinFET n阱和p阱一起植入。

7. 发明申请

US20130307516A1 BANDGAP REFERENCE CIRCUIT 有权
标题翻译：带宽参考电路
公开(公告)号：US20130307516A1
公开(公告)日：2013-11-21
申请号：US13472063
申请日：2012-05-15
申请人： Jaw-Juinn HORNG , Kuo-Feng YU , Chung-Hui CHEN
发明人： Jaw-Juinn HORNG , Kuo-Feng YU , Chung-Hui CHEN
IPC分类号： G05F3/02
CPC分类号： G05F3/16 , G05F3/30
摘要： A bandgap reference circuit including two sets of bipolar junction transistors (BJTs). A first set of two or more BJTs configured to electrically connect in a parallel arrangement. The first set of BJTs is configured to produce a first proportional to absolute temperature (PTAT) signal. A second set of two or more BJTs configured to electrically connect in a parallel arrangement. The second set of BJTs is configured to produce a second PTAT signal. A circuitry configured to electrically connect to the first set of BJTs and the second set of BJTs. The circuitry is configured to combine the first PTAT signal and the second PTAT signal to produce a reference voltage.
摘要翻译：一种带隙参考电路，包括两组双极结型晶体管（BJT）。配置为以并联布置电连接的第一组两个或更多个BJT。第一组BJT被配置为产生与绝对温度（PTAT）信号成比例的第一比例。第二组两个或多个BJT被配置为以并联布置电连接。第二组BJT被配置为产生第二PTAT信号。一种被配置为电连接到第一组BJT和第二组BJT的电路。电路被配置为组合第一PTAT信号和第二PTAT信号以产生参考电压。

8. 发明申请

US20130027105A1 NON-OVERLAP CIRCUIT 有权
标题翻译：非重叠电路
公开(公告)号：US20130027105A1
公开(公告)日：2013-01-31
申请号：US13193660
申请日：2011-07-29
申请人： Jaw-Juinn HORNG
发明人： Jaw-Juinn HORNG
IPC分类号： H03H11/26
CPC分类号： H03K5/1515 , H03K17/102 , H03K17/162
摘要： A non-overlap circuit includes a first delay circuit configured to receive a first input signal and output a first control signal to a driver circuit, sensing circuitry configured to sense a current generated in response to the first control signal coupled through bulk semiconductor of a semiconductor substrate and produce a feedback signal response, and a second delay circuit. The second delay circuit configured to receive the feedback signal from the sensing circuitry and a second input signal and output a second control signal to the driver circuit based on the sensed feedback signal and the second input signal.
摘要翻译：非重叠电路包括被配置为接收第一输入信号并将第一控制信号输出到驱动器电路的第一延迟电路，感测电路被配置为感测响应于通过半导体的体半导体耦合的第一控制信号而产生的电流衬底并产生反馈信号响应，以及第二延迟电路。第二延迟电路被配置为从感测电路接收反馈信号和第二输入信号，并且基于感测到的反馈信号和第二输入信号将第二控制信号输出到驱动器电路。

9. 发明申请

US20130162331A1 DIODE STRING VOLTAGE ADAPTER 有权
标题翻译：二极管电压适配器
公开(公告)号：US20130162331A1
公开(公告)日：2013-06-27
申请号：US13336563
申请日：2011-12-23
申请人： Chung-Peng HSIEH , Jaw-Juinn HORNG
发明人： Chung-Peng HSIEH , Jaw-Juinn HORNG
IPC分类号： H03K3/01 , H01L27/04
CPC分类号： H01L27/0814
摘要： A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.
摘要翻译：二极管串电压适配器包括形成在第一导电类型的衬底中的二极管。每个二极管包括在衬底中形成的第二导电类型的深阱区。第一导电类型的第一阱区形成在深阱区上。形成在第一阱区上的第一导电类型的第一重掺杂区。形成在第一阱区上的第二导电类型的第二重掺杂区。二极管彼此串联耦合。开始二极管的第一重掺杂区域耦合到第一电压。每个二极管的第二重掺杂区域被耦合到下一个二极管的第一重掺杂区域。末端二极管的第二重掺杂区域提供第二电压。深井区被配置为电浮动。

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