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1. 发明申请

US20140008817A1 THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT 审中-公开
标题翻译：通过硅（TSV）隔离结构减少3D集成电路中的噪声
公开(公告)号：US20140008817A1
公开(公告)日：2014-01-09
申请号：US14024925
申请日：2013-09-12
申请人： Jaw-Juinn HORNG , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
发明人： Jaw-Juinn HORNG , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
摘要翻译：提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能通过半导体衬底传播的电噪声。隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

2. 发明授权

US08546953B2 Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit 有权
标题翻译：通过硅通孔（TSV）隔离结构降低3D集成电路
公开(公告)号：US08546953B2
公开(公告)日：2013-10-01
申请号：US13324405
申请日：2011-12-13
申请人： Jaw-Juinn Horng , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
发明人： Jaw-Juinn Horng , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
IPC分类号： H01L23/48 , H01L29/40 , H01L23/04 , H01L21/44
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
摘要翻译：提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能传播通过半导体衬底的电噪声。隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

3. 发明授权

US08878369B2 Low power/high speed TSV interface design 有权
标题翻译：低功耗/高速TSV接口设计
公开(公告)号：US08878369B2
公开(公告)日：2014-11-04
申请号：US13546024
申请日：2012-07-11
申请人： Chung-Hui Chen , Jaw-Juinn Horng , Shuo-Mao Chen , Der-Chyang Yeh
发明人： Chung-Hui Chen , Jaw-Juinn Horng , Shuo-Mao Chen , Der-Chyang Yeh
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L25/065 , H01L23/14 , H01L23/498
CPC分类号： H01L25/0657 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L2225/06572 , H01L2924/0002 , H01L2924/00
摘要： A TSV interface circuit for a TSV provided in an interposer substrate that forms a connection between a first die and a second die includes a driving circuit provided in the first die and a receiver circuit provided in the second die where the driving circuit is coupled to a first supply voltage and a second supply voltage that are both lower than the interposer substrate voltage that substantially reduces the parasitic capacitance of the TSV. The receiver circuit is also coupled to the first supply voltage and the second supply voltage that are both lower than the interposer substrate voltage.
摘要翻译：设置在形成第一管芯和第二管芯之间的连接的插入器基板中的TSV的TSV接口电路包括设置在第一管芯中的驱动电路和设置在第二管芯中的接收器电路，其中驱动电路耦合到第一电源电压和第二电源电压均低于基本上降低TSV的寄生电容的插入器基板电压。接收器电路还耦合到低于插入器基板电压的第一电源电压和第二电源电压。

4. 发明授权

US09612606B2 Bandgap reference circuit 有权
公开(公告)号：US09612606B2
公开(公告)日：2017-04-04
申请号：US13472063
申请日：2012-05-15
申请人： Jaw-Juinn Horng , Kuo-Feng Yu , Chung-Hui Chen
发明人： Jaw-Juinn Horng , Kuo-Feng Yu , Chung-Hui Chen
IPC分类号： G05F3/30
CPC分类号： G05F3/16 , G05F3/30
摘要： A bandgap reference circuit including two sets of bipolar junction transistors (BJTs). A first set of two or more BJTs configured to electrically connect in a parallel arrangement. The first set of BJTs is configured to produce a first proportional to absolute temperature (PTAT) signal. A second set of two or more BJTs configured to electrically connect in a parallel arrangement. The second set of BJTs is configured to produce a second PTAT signal. A circuitry configured to electrically connect to the first set of BJTs and the second set of BJTs. The circuitry is configured to combine the first PTAT signal and the second PTAT signal to produce a reference voltage.

5. 发明授权

US08610241B1 Homo-junction diode structures using fin field effect transistor processing 有权
标题翻译：使用鳍式场效应晶体管处理的同相二极管结构
公开(公告)号：US08610241B1
公开(公告)日：2013-12-17
申请号：US13494795
申请日：2012-06-12
申请人： Chia-Hsin Hu , Sun-Jay Chang , Jaw-Juinn Horng , Chung-Hui Chen
发明人： Chia-Hsin Hu , Sun-Jay Chang , Jaw-Juinn Horng , Chung-Hui Chen
IPC分类号： H01L21/70
CPC分类号： H01L27/0623 , H01L27/0629 , H01L27/0635 , H01L27/0664 , H01L27/0814 , H01L29/861
摘要： Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.
摘要翻译：通过在FinFET形成过程中利用各种工艺步骤，在包括鳍状场效应晶体管（FinFET）的IC器件中形成二极管和双极结型晶体管（BJT）。二极管或BJT包括具有不同深度的n阱的隔离散热片区域和散热片阵列区域，以及围绕隔离鳍片区域中的n阱的散热片阵列区域的一部分中的p阱。二极管和BJT的n阱和p阱与FinFET n阱和p阱一起植入。

6. 发明授权

US08736355B2 Device layout for reference and sensor circuits 有权
标题翻译：参考和传感器电路的器件布局
公开(公告)号：US08736355B2
公开(公告)日：2014-05-27
申请号：US13494060
申请日：2012-06-12
申请人： Jaw-Juinn Horng , Chung-Hui Chen , Sun-Jay Chang , Chia-Hsin Hu
发明人： Jaw-Juinn Horng , Chung-Hui Chen , Sun-Jay Chang , Chia-Hsin Hu
IPC分类号： G05F1/10
CPC分类号： H01L27/0814 , H01L27/0207
摘要： A band gap reference circuit includes an error-amplifier-based current mirror coupled between a first supply node and a pair of intermediate voltage nodes, and a matched diode pair for providing a proportional-to-absolute temperature (PTAT) current. The matched diode pair includes a first diode connected between a first intermediate voltage node from the pair of intermediate voltage nodes and a second supply node, and a second diode connected in series with a resistor between a second intermediate voltage node from the pair of intermediate voltage nodes and the second supply node. Each diode has a P-N diode junction that is a homojunction.
摘要翻译：带隙参考电路包括耦合在第一电源节点和一对中间电压节点之间的基于误差放大器的电流镜，以及用于提供比例绝对温度（PTAT）电流的匹配二极管对。匹配二极管对包括连接在来自一对中间电压节点的第一中间电压节点和第二电源节点之间的第一二极管，以及与来自所述一对中间电压的第二中间电压节点之间的电阻器串联连接的第二二极管节点和第二个供应节点。每个二极管具有一个同相结合的P-N二极管结。

7. 发明授权

US09287252B2 Semiconductor mismatch reduction 有权
标题翻译：半导体失配减少
公开(公告)号：US09287252B2
公开(公告)日：2016-03-15
申请号：US13048411
申请日：2011-03-15
申请人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
发明人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
IPC分类号： H01L29/12 , H01L27/02
CPC分类号： H01L27/0207
摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
摘要翻译：公开了一种用于减小密度失配的系统和方法。一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

8. 发明申请

US20120235208A1 Semiconductor Mismatch Reduction 有权
标题翻译：半导体失配减少
公开(公告)号：US20120235208A1
公开(公告)日：2012-09-20
申请号：US13048411
申请日：2011-03-15
申请人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
发明人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
IPC分类号： H01L29/12 , H01L21/66
CPC分类号： H01L27/0207
摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
摘要翻译：公开了一种用于减小密度失配的系统和方法。一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

9. 发明授权

US08850379B2 Method of and system for generating optimized semiconductor component layout 有权
标题翻译：用于生成优化的半导体元件布局的方法和系统
公开(公告)号：US08850379B2
公开(公告)日：2014-09-30
申请号：US13352738
申请日：2012-01-18
申请人： Chien-Hung Chen , Yung-Chow Peng , Chung-Hui Chen , Chih Ming Yang
发明人： Chien-Hung Chen , Yung-Chow Peng , Chung-Hui Chen , Chih Ming Yang
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F2217/02 , G06F2217/06 , G06F2217/08 , G06F2217/12 , H01L27/0207 , H01L29/94
摘要： A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components.
摘要翻译：根据一组设计规则生成半导体部件的优化布局的方法包括为包括一个或多个半导体部件的单元单元生成多个配置，每个配置满足设计规则的一些但不是全部。对于每个配置，检查作为单位单元的重复图案的布局是否满足剩余的设计规则。在满足所有设计规则的配置中，选择提供最佳的属性值的配置用于生成半导体部件的优化布局。

10. 发明授权

US08803320B2 Integrated circuits and fabrication methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08803320B2
公开(公告)日：2014-08-12
申请号：US13025763
申请日：2011-02-11
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H01L29/40
CPC分类号： H01L23/552 , H01L23/5225 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a signal line routed in a first direction. A first shielding pattern is disposed substantially parallel with the signal line. The first shielding pattern has a first edge having a first dimension and a second edge having a second dimension. The first edge is substantially parallel with the signal line. The first dimension is larger than the second dimension. A second shielding pattern is disposed substantially parallel with the signal line. The second shielding pattern has a third edge having a third dimension and a fourth edge having a fourth dimension. The third edge is substantially parallel with the signal line. The third dimension is larger than the fourth dimension. The fourth edge faces the second edge. A first space is between the second and fourth edges.
摘要翻译：集成电路包括沿第一方向布线的信号线。第一屏蔽图案基本上与信号线平行设置。第一屏蔽图案具有具有第一尺寸的第一边缘和具有第二尺寸的第二边缘。第一边缘基本上与信号线平行。第一个维度大于第二个维度。第二屏蔽图案基本上与信号线平行设置。第二屏蔽图案具有具有第三尺寸的第三边缘和具有第四尺寸的第四边缘。第三边缘基本上与信号线平行。第三维度大于第四维度。第四个边缘面向第二个边缘。第一空间在第二和第四边之间。

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