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1. 发明申请

US20130006561A1 COMPUTING DEVICE, STORAGE MEDIUM, AND METHOD FOR ANALYZING SIGNAL GROUP DELAY OF PRINTED CIRCUIT BOARD 审中-公开
标题翻译：计算机设备，存储介质和分析印刷电路板信号组延迟的方法
公开(公告)号：US20130006561A1
公开(公告)日：2013-01-03
申请号：US13451433
申请日：2012-04-19
申请人： PO-CHUAN HSIEH , CHUN-JEN CHEN , YING-TSO LAI , EN-SHUO CHANG
发明人： PO-CHUAN HSIEH , CHUN-JEN CHEN , YING-TSO LAI , EN-SHUO CHANG
IPC分类号： G06F19/00
CPC分类号： G06F17/5036 , G06F17/5068 , G06F2217/62 , G06F2217/82
摘要： In a method for analyzing a signal group delay of a printed circuit board (PCB) using a computing device, the computing device connects to a signal measuring device that measures S-parameters from a pair of data signal line and clock signal line of the PCB. The method analyzes a differential loss coefficient of the data signal line and the clock signal line based on the S-parameters, and calculates a first signal delay of the data signal line and a second signal delay of the clock signal line according to the differential loss coefficient. The method further analyzes a signal group delay of the PCB according to the first signal delay and the second signal delay, and displays the signal group delay on a display device if the signal group delay does not satisfy a PCB design specification.
摘要翻译：在使用计算设备分析印刷电路板（PCB）的信号组延迟的方法中，计算设备连接到从PCB的一对数据信号线和时钟信号线测量S参数的信号测量装置。该方法基于S参数分析数据信号线和时钟信号线的差分损耗系数，并根据差分损耗计算数据信号线的第一信号延迟和时钟信号线的第二信号延迟系数。该方法还根据第一信号延迟和第二信号延迟分析PCB的信号组延迟，并且如果信号组延迟不满足PCB设计规范，则在显示装置上显示信号组延迟。

2. 发明申请

US20110284279A1 PRINTED CIRCUIT BOARD 失效
标题翻译：印刷电路板
公开(公告)号：US20110284279A1
公开(公告)日：2011-11-24
申请号：US12790883
申请日：2010-05-31
申请人： YING-TSO LAI , YUNG-CHIEH CHEN , CHUN-JEN CHEN , WEI-CHIEH CHOU
发明人： YING-TSO LAI , YUNG-CHIEH CHEN , CHUN-JEN CHEN , WEI-CHIEH CHOU
IPC分类号： H05K1/11
CPC分类号： H05K1/0225 , H05K1/0245 , H05K1/0253
摘要： A printed circuit board includes a signal layer, a dielectric layer, and a reference layer. The signal layer includes a pair of differential signal lines. The dielectric layer is sandwiched between the signal layer and the reference layer. A first void is defined in the reference layer between projections of the pair of differential signal lines. Two second voids are defined in the reference layer at opposite sides of the projections of the pair of differential signal lines.
摘要翻译：印刷电路板包括信号层，电介质层和参考层。信号层包括一对差分信号线。电介质层夹在信号层和参考层之间。在该对差分信号线的投影之间的参考层中限定第一空隙。在该对差分信号线的突起的相对侧的参考层中限定两个第二空隙。

3. 发明申请

US20120090884A1 PRINTED CIRCUIT BOARD 审中-公开
标题翻译：印刷电路板
公开(公告)号：US20120090884A1
公开(公告)日：2012-04-19
申请号：US12981460
申请日：2010-12-29
申请人： TSUNG-SHENG HUANG , YING-TSO LAI , CHUN-JEN CHEN , WEI-CHIEH CHOU
发明人： TSUNG-SHENG HUANG , YING-TSO LAI , CHUN-JEN CHEN , WEI-CHIEH CHOU
IPC分类号： H05K1/11
CPC分类号： H05K1/0265 , H05K1/0201 , H05K1/116 , H05K2201/09309
摘要： A printed circuit board includes a plurality of power layers. Each power layer defining a number of vias arranged in a number of rows. The number of the power layers is N (N>3). The power layers are defined as a 1st, 2nd, . . . , Nth power layer. The vias of the 1st power layer are connected to other power layers by a step-shaped connection means.
摘要翻译：印刷电路板包括多个功率层。每个功率层定义了以多行布置的多个通孔。功率层的数量为N（N> 3）。功率层定义为1，2，...。。。，第N功率层。第一功率层的通孔通过阶梯形连接装置连接到其它功率层。

4. 发明申请

US20110094787A1 PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：印刷电路板及其制造方法
公开(公告)号：US20110094787A1
公开(公告)日：2011-04-28
申请号：US12647431
申请日：2009-12-25
申请人： YING-TSO LAI , CHUN-JEN CHEN , YU-CHANG PAI , PEI-CHUN LIN , CHIN-HUI CHEN , HSIAO-PING HUANG
发明人： YING-TSO LAI , CHUN-JEN CHEN , YU-CHANG PAI , PEI-CHUN LIN , CHIN-HUI CHEN , HSIAO-PING HUANG
IPC分类号： H05K1/11 , H05K3/10
CPC分类号： H05K1/116 , H05K1/0201 , H05K3/3447 , H05K2201/062 , H05K2201/09036 , H05K2201/093 , H05K2201/0969 , H05K2203/0242 , Y10T29/49155
摘要： A printed circuit board includes a layer. A layer of copper is covered on a surface of the layer. A through hole passes through the printed circuit board. A number of thermal engravings are defined in the layer around the through hole. Each thermal engraving is a groove defined in the surface of the layer, without covered with the layer of copper. The number of thermal engravings are not in contact with each other.
摘要翻译：印刷电路板包括一层。铜层被覆盖在该层的表面上。通孔穿过印刷电路板。在通孔周围的层中限定了许多热雕刻。每个热雕刻是在层的表面中限定的凹槽，而不被铜层覆盖。热雕刻的数量彼此不接触。

5. 发明申请

US20130284508A1 PRINTED CIRCUIT BOARD 审中-公开
标题翻译：印刷电路板
公开(公告)号：US20130284508A1
公开(公告)日：2013-10-31
申请号：US13563856
申请日：2012-08-01
申请人： WEI-CHIEH CHOU , CHUN-JEN CHEN , DUEN-YI HO , TSUNG-SHENG HUANG , PO-CHUAN HSIEH , CHUN-NENG LIAO
发明人： WEI-CHIEH CHOU , CHUN-JEN CHEN , DUEN-YI HO , TSUNG-SHENG HUANG , PO-CHUAN HSIEH , CHUN-NENG LIAO
IPC分类号： H05K1/11
CPC分类号： H05K1/0216 , H05K2201/09618
摘要： A printed circuit board (PCB) includes a power layer and a signal layer. A signal line is arranged on the signal layer. A power via extends through the power layer and the signal layer, and is electrically connected to the power layer and the signal layer. A number of through holes is defined in the PCB, through the power layer and the signal layer, and arranged between the signal line and the power via. The through holes are insulated from the power via. The inside wall of the power via is made of conductive material.
摘要翻译：印刷电路板（PCB）包括功率层和信号层。信号线布置在信号层上。功率通孔延伸通过功率层和信号层，并且电连接到功率层和信号层。在PCB中通过功率层和信号层定义了多个通孔，并布置在信号线和电源通孔之间。通孔与电源通孔绝缘。电源通孔的内壁由导电材料制成。

6. 发明申请

US20110051793A1 SYSTEM AND METHOD FOR EVALUATING PERFORMANCE OF A MIMO ANTENNA SYSTEM 失效
标题翻译：用于评估MIMO天线系统性能的系统和方法
公开(公告)号：US20110051793A1
公开(公告)日：2011-03-03
申请号：US12633895
申请日：2009-12-09
申请人： PO-CHUAN HSIEH , CHUN-JEN CHEN , CHIEN-HUNG LIU , YU-CHANG PAI , SHOU-KUO HSU
发明人： PO-CHUAN HSIEH , CHUN-JEN CHEN , CHIEN-HUNG LIU , YU-CHANG PAI , SHOU-KUO HSU
IPC分类号： H04B17/00
CPC分类号： H04B17/0085 , H04B17/21 , H04B17/23 , H04B17/327 , H04L1/0668
摘要： A performance evaluation system for a multiple-input multiple-output (MIMO) antenna system receives simulation parameters from an input device, and simulates a MIMO antenna system accordingly. A method, also provided, further evaluates performance of the simulated MIMO antenna system when a series of radio frequency (RF) signals are transmitted through the MIMO antenna system, and displays a performance analysis result of the MIMO antenna system on a display device for evaluation of the performance of the simulated MIMO antenna system.
摘要翻译：用于多输入多输出（MIMO）天线系统的性能评估系统从输入设备接收模拟参数，并相应地模拟MIMO天线系统。还提供了一种方法，当通过MIMO天线系统传输一系列射频（RF）信号时，进一步评估模拟MIMO天线系统的性能，并且在用于评估的显示装置上显示MIMO天线系统的性能分析结果的模拟MIMO天线系统的性能。

7. 发明申请

US20130055190A1 COMPUTING DEVICE AND METHOD FOR CHECKING DESIGN OF PRINTED CIRCUIT BOARD LAYOUT FILE 失效
标题翻译：打印电路板布局文件设计的计算装置及方法
公开(公告)号：US20130055190A1
公开(公告)日：2013-02-28
申请号：US13523874
申请日：2012-06-14
申请人： DAN-CHEN WU , SHOU-KUO HSU , CHUN-JEN CHEN
发明人： DAN-CHEN WU , SHOU-KUO HSU , CHUN-JEN CHEN
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/78
摘要： A computing device reads a printed circuit board (PCB) layout file from a storage device. The PCB layout file includes arrangement information of signal lines, power lines, and power through-holes arranged on a PCB. Furthermore, the computing device sets a reference distance between a selected power through-hole and a neighboring signal line, and searches for one or more line segments of one or more signal lines where the a distance between each of the one or more line segment and the selected power through-hole is less than the reference distance.
摘要翻译：计算设备从存储设备读取印刷电路板（PCB）布局文件。 PCB布局文件包括布置在PCB上的信号线，电源线和电源通孔的布置信息。此外，计算装置设置所选功率通孔和相邻信号线之间的参考距离，并且搜索一个或多个信号线的一个或多个线段，其中，所述一个或多个线段中的每一个之间的距离和所选功率通孔小于参考距离。

8. 发明申请

US20120268086A1 POWER SUPPLY DEVICE 失效
标题翻译：电源设备
公开(公告)号：US20120268086A1
公开(公告)日：2012-10-25
申请号：US13340707
申请日：2011-12-30
申请人： WEI-CHIEH CHOU , DUEN-YI HO , CHUN-JEN CHEN , TSUNG-SHENG HUANG
发明人： WEI-CHIEH CHOU , DUEN-YI HO , CHUN-JEN CHEN , TSUNG-SHENG HUANG
IPC分类号： G05F1/12 , H03F3/45
CPC分类号： H02M3/33523 , H02M2001/0003
摘要： A power supply device includes a power supply unit and a feedback control unit. The power supply unit is configured for generating an electric potential to be provided to a load. The feedback control unit detects the electric potential and adjusts relevant parameters of the electrical potential to achieve predetermined values. The feedback control unit includes a first feedback circuit and a second feedback circuit electrically connected in series.
摘要翻译：电源装置包括电源单元和反馈控制单元。电源单元被配置为产生要提供给负载的电位。反馈控制单元检测电位并调整电位的相关参数以实现预定值。反馈控制单元包括串联电连接的第一反馈电路和第二反馈电路。

9. 发明申请

US20110238233A1 SYSTEM AND METHOD FOR OPTIMIZING CURRENT OVERLOAD PROTECTION CIRCUIT 失效
标题翻译：用于优化电流过载保护电路的系统和方法
公开(公告)号：US20110238233A1
公开(公告)日：2011-09-29
申请号：US12774685
申请日：2010-05-05
申请人： TSUNG-SHENG HUANG , CHUN-JEN CHEN , DUEN-YI HO , WEI-CHIEH CHOU
发明人： TSUNG-SHENG HUANG , CHUN-JEN CHEN , DUEN-YI HO , WEI-CHIEH CHOU
IPC分类号： G06F19/00
CPC分类号： G06F17/5063
摘要： A system for optimizing a current overload protection circuit includes an input device, a data storage device, a central processing device, and a display. The central processing device includes a storage module, a control module, and a calculation module. The storage module stores a VI application therein. The control module receives instructions from the input device and selects virtual electronic components of the current overload protection circuit from the data storage device and connection of the selected electronic components. The current overload protection circuit is completed and run in the VI application; electronic components significantly affecting the maximum protection current are labeled. The calculation module calculates normal distribution samples of the current overload protection circuit based on the labeled electronic components. The display shows whether the current overload protection circuit meets a process capability standard.
摘要翻译：用于优化电流过载保护电路的系统包括输入装置，数据存储装置，中央处理装置和显示器。中央处理装置包括存储模块，控制模块和计算模块。存储模块在其中存储VI应用。控制模块从输入设备接收指令，并从数据存储设备中选择电流过载保护电路的虚拟电子部件，并选择电子部件的连接。电流过载保护电路在VI应用中完成并运行; 显着影响最大保护电流的电子元件被标记。计算模块基于标记的电子元件计算电流过载保护电路的正态分布样本。显示屏显示电流过载保护电路是否符合过程能力标准。

10. 发明申请

US20120297356A1 COMPUTING DEVICE AND METHOD FOR INSPECTING LAYOUT OF PRINTED CIRCUIT BOARD 失效
标题翻译：用于检查印刷电路板布局的计算装置和方法
公开(公告)号：US20120297356A1
公开(公告)日：2012-11-22
申请号：US13213072
申请日：2011-08-18
申请人： DAN-CHEN WU , SHOU-KUO HSU , CHENG-HSIEN LEE , CHUN-JEN CHEN
发明人： DAN-CHEN WU , SHOU-KUO HSU , CHENG-HSIEN LEE , CHUN-JEN CHEN
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： In a method for inspecting the layout of a printed circuit board (PCB), a component to be checked is determined from an electronic layout diagram of the PCB, and a power transmission line which may be serving that component is selected. The layout diagram is checked to determine whether the component is connected to the power transmission line, and further checked to determine whether more than one ground pins of the component is connected to the power transmission line. Vias that are shared by two or more ground pins of the component are determined if more than one ground pin is connected to the power transmission line. Shared vias are marked on the layout diagram.
摘要翻译：在用于检查印刷电路板（PCB）的布局的方法中，从PCB的电子布局图确定要检查的部件，并且可以选择可用于该部件的输电线。检查布局图以确定组件是否连接到电力传输线，并进一步检查以确定组件的多个接地引脚是否连接到电力传输线。如果多个接地引脚连接到电力传输线，则确定由组件的两个或更多个接地引脚共享的通孔。共享通孔在布局图上标出。

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