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1. 发明授权

US4653025A Random access memory with high density and low power 失效
标题翻译：具有高密度和低功耗的随机存取存储器
公开(公告)号：US4653025A
公开(公告)日：1987-03-24
申请号：US685132
申请日：1984-12-21
申请人： Osamu Minato , Masakazu Aoki , Yuji Yatsuda , Katsuaki Takagi , Masashi Horiguchi
发明人： Osamu Minato , Masakazu Aoki , Yuji Yatsuda , Katsuaki Takagi , Masashi Horiguchi
IPC分类号： H01L27/00 , G11C11/412 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/10 , H01L27/11 , G11C11/40
CPC分类号： G11C11/412
摘要： A static RAM having a plurality of memory cells. Each memory cell consists of driver MOST's that are connected to each other in a crossing manner, and transfer MOST's that connect storage nodes of the memory cell to the data lines. The driver MOST's are comprised of n-channel MOST's, and the transfer MOST's are comprised of p-channel MOST's.
摘要翻译：具有多个存储单元的静态RAM。每个存储器单元由以交叉方式彼此连接的驱动器MOST组成，并且传送将存储器单元的存储节点连接到数据线的MOST。驱动器MOST由n沟道MOST组成，传输MOST由p沟道MOST组成。

2. 发明授权

US4701884A Semiconductor memory for serial data access 失效
标题翻译：用于串行数据访问的半导体存储器
公开(公告)号：US4701884A
公开(公告)日：1987-10-20
申请号：US896257
申请日：1986-08-14
申请人： Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Katsuhiro Shimohigashi , Toshiaki Masuhara , Kiyoo Itoh , Hideo Nakamura , Osamu Minato
发明人： Masakazu Aoki , Masashi Horiguchi , Yoshinobu Nakagome , Shinichi Ikenaga , Katsuhiro Shimohigashi , Toshiaki Masuhara , Kiyoo Itoh , Hideo Nakamura , Osamu Minato
IPC分类号： G11C11/56 , H01L27/108 , G11C13/00
CPC分类号： G11C11/565 , H01L27/10805
摘要： A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided. The feature of this device lies in that the voltage generator for serially generating three or more values of the voltage which are different from each other and the means for applying said voltage to said memory cells are provided on the same semiconductor board as the same said memory cells, and as the said reading mechanism the column register is provided which, as said reading mechanism, has the mechanism for deciding the data, transfer gate which is provided between said deciding means and said data line, and the bias charge transfer mechanism which is provided between said transfer gate and said deciding mechanism, and having at least two or more memory elements for temporarily storing said decided data.
摘要翻译：提出了一种半导体存储器件，其中至少包括多个具有至少一个容量的存储单元的阵列，用于指定每个存储单元的位置的选择机构，连接到所述存储器单元的用于发送数据的数据线和数据提供写入和数据读取机制。该装置的特征在于，用于串联产生彼此不同的三个或更多个电压值的电压发生器和用于将所述电压施加到所述存储单元的装置设置在与所述存储器相同的半导体板上并且作为所述读取机构，列寄存器被提供，其作为所述读取机构具有用于确定数据的机制，所述决定装置和所述数据线之间提供的传送门和作为所述读取机构的偏置电荷传送机构提供在所述传送门和所述判定机构之间，并且具有用于临时存储所述决定的数据的至少两个或更多个存储器元件。

3. 发明授权

US5483083A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5483083A
公开(公告)日：1996-01-09
申请号：US028128
申请日：1993-03-09
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.
摘要翻译：提供采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET上方。存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由与驱动MISFET的不同层导电膜组成的栅电极组成。在用于将地电位施加到其驱动MISFET的源极区的存储单元的驱动和负载MISFET的堆叠布置中，形成作为单独导电层的布线。

4. 发明授权

US4992677A High speed MOSFET output buffer with low noise 失效
标题翻译：高速MOSFET输出缓冲器，噪音低
公开(公告)号：US4992677A
公开(公告)日：1991-02-12
申请号：US325439
申请日：1989-03-20
申请人： Koichiro Ishibashi , Osamu Minato , Katsuhiro Shimohigashi
发明人： Koichiro Ishibashi , Osamu Minato , Katsuhiro Shimohigashi
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K17/166 , H03K19/00361
摘要： A semiconductor integrated circuit includes: a data output terminal; a first semiconductor element connected between a first operating potential point and the data output terminal; a second semiconductor element connected between the data output terminal and a second operating potential point; first control means connected to a control input terminal of the first semiconductor element; second control means connected to a control input terminal of the second semiconductor element; first generating means for generating a first predetermined voltage; and second generating means for generating a second predetermined voltage higher than the first predetermined voltage. When voltage at the data output terminal is higher than the second predetermined voltage, the first control means controls the first semiconductor element to be in the OFF-state, and the second control means controls the second semiconductor element to be in the ON-state to lower the voltage of the data output terminal to the second predetermined voltage. On the other hand, in the case where the voltage of the data output terminal is lower than that of the first predetermined voltage, the output of the first control means controls the first semiconductor element so that it is in the ON-state and the output of the second control means controls the second semiconductor element so that it is in the OFF-state so as to raise the voltage of the data output terminal to the first predetermined voltage.
摘要翻译：半导体集成电路包括：数据输出端子; 连接在第一操作电位点和数据输出端之间的第一半导体元件; 连接在数据输出端和第二工作电位之间的第二半导体元件; 连接到第一半导体元件的控制输入端的第一控制装置; 连接到第二半导体元件的控制输入端子的第二控制装置; 用于产生第一预定电压的第一产生装置; 以及第二产生装置，用于产生高于第一预定电压的第二预定电压。当数据输出端子的电压高于第二预定电压时，第一控制装置控制第一半导体元件处于截止状态，第二控制装置将第二半导体元件控制在导通状态将数据输出端子的电压降低到第二预定电压。另一方面，在数据输出端子的电压低于第一预定电压的电压的情况下，第一控制装置的输出控制第一半导体元件使其处于导通状态并且输出所述第二控制装置控制所述第二半导体元件使其处于截止状态，以将所述数据输出端子的电压升高到所述第一预定电压。

5. 发明授权

US4935901A Semiconductor memory with divided bit load and data bus lines 失效
公开(公告)号：US4935901A
公开(公告)日：1990-06-19
申请号：US158259
申请日：1988-02-19
申请人： Toshio Sasaki , Osamu Minato , Shigeru Honjiyo , Koichiro Ishibashi , Toshiaki Masuhara
发明人： Toshio Sasaki , Osamu Minato , Shigeru Honjiyo , Koichiro Ishibashi , Toshiaki Masuhara
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： A static RAM memory is divided into a plurality of mats (12). Word lines (16) in each pair of mats are accessed by an x-decoder (14). Columns or bit lines are accessed by a y-decoder (20) which selectively connect pairs of bit lines (22) to common data bus segments (24). Transistors (60, 62) connect selected bit lines with a load during a write cycle to stabilize those bit lines and memory cells into which data is written. The x-decoders are connected with near word lines (16a) for addressing a near half of each mat and are operatively connected with remote word lines (16b) for addressing word lines in a remote half of each mat. In this manner, each mat is divided into two effective mats. The bit lines of all the effective mats within an actual mat are connected with the same output data bus segment. A pair of sensing amplifiers (32) is provided for each bit of memory which is accessed concurrently, e.g. eight bits, such that the high and low output of each flip-flop memory cell (18) are both amplified. A pair of driving amplifiers (34) further amplify each high and low output before applying them to an output data bus (38).

6. 发明授权

US4539660A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US4539660A
公开(公告)日：1985-09-03
申请号：US331278
申请日：1981-12-16
申请人： Katsuki Miyauchi , Tetsuichi Kudo , Osamu Minato , Toshiaki Masuhara , Yoshio Uetani
发明人： Katsuki Miyauchi , Tetsuichi Kudo , Osamu Minato , Toshiaki Masuhara , Yoshio Uetani
IPC分类号： H02J7/00 , G06F1/00 , G06F1/26 , G06F12/16 , G11C5/14 , G11C11/413 , H01B5/14 , H01L21/336 , H01L21/8247 , H01L23/495 , H01L25/00 , H01L27/105 , H01L29/788 , H01L29/792 , H01M2/10 , H01M4/58 , H01M10/052 , H01M10/0562 , H01M10/44 , H02J1/00 , H02J7/34 , G11C11/34
CPC分类号： H01M10/0562 , G11C5/141 , H01L23/49593 , H01M2/1066 , H01L2224/49171 , H01L24/49 , H01L2924/00014 , H01L2924/01014 , H01L2924/10253 , H01L2924/14 , H01L2924/19041
摘要： A nonvolatile memory in which at least one power supply element is carried with an integrated circuit chip containing the memory and connected to power supply terminals of the integrated circuit chip having a memory cell array in which a plurality of memory elements or memory circuits are arrayed.
摘要翻译：一种非易失性存储器，其中至少一个电源元件被携带有集成电路芯片，所述集成电路芯片包含所述存储器并且连接到所述集成电路芯片的电源端子，所述集成电路芯片具有其中排列有多个存储器元件或存储器电路的存储单元阵列。

7. 发明授权

US4086642A Protective circuit and device for metal-oxide-semiconductor field effect transistor and method for fabricating the device 失效
标题翻译：用于金属氧化物半导体场效应晶体管的保护电路和器件及其制造方法
公开(公告)号：US4086642A
公开(公告)日：1978-04-25
申请号：US648714
申请日：1976-01-13
申请人： Isao Yoshida , Ryoichi Hori , Hiroo Masuda , Osamu Minato , Jun Etoh , Masaaki Nakai
发明人： Isao Yoshida , Ryoichi Hori , Hiroo Masuda , Osamu Minato , Jun Etoh , Masaaki Nakai
IPC分类号： H01L27/02 , H01L27/06 , H01L29/417 , H01L29/78 , H02H7/20 , H03F1/42 , H03F1/52 , H03K17/0812 , H02H9/04
CPC分类号： H03K17/08122 , H01L27/0266 , H03F1/523
摘要： A protective circuit comprises a metal-oxide-semiconductor field effect transistor (MOSFET) to be protected, and a depletion-type MOSFET the gate and source of which are connected to each other and the souce of which is connected to the gate of the MOSFET to be protected, whereby the protective circuit which is suitable for a high-speed operation is completed.
摘要翻译：保护电路包括要被保护的金属氧化物半导体场效应晶体管（MOSFET），以及栅极和源极彼此连接的漏极型MOSFET，其漏极连接到MOSFET的栅极被保护，从而完成适合于高速操作的保护电路。

8. 发明授权

US5619055A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5619055A
公开(公告)日：1997-04-08
申请号：US429882
申请日：1995-04-27
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/76
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error. The overlapping relationship for effecting the large capacitor element across the source and gate of the respective load MISFETs is provided by an ion implanting scheme of a p-type impurity into the semiconductor strip. A separate mask for ion-implantation for the formation of the source region of the load MISFET is added followed by the addition of the gate electrode thereof in a manner so as to have a widely overlapping relationship with that of the source region.
摘要翻译：公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET之上。存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由不同于导电膜的驱动MISFET组成的栅电极构成。在具有这种堆叠布置的存储器单元中，每个负载MISFET的源极区域和栅电极被图案化以具有彼此广泛重叠的关系，以形成电容器元件，使得与每个负载MISFET相关联的总体电容的增加存储单元存储节点被实现，从而减少软错误的发生。通过p型杂质离子注入到半导体条中的方式来提供跨越各个负载MISFET的源极和栅极的大电容器元件的重叠关系。添加用于形成负载MISFET的源极区域的离子注入的单独的掩模，然后以与源极区域具有广泛重叠的关系的方式添加其栅电极。

9. 发明授权

US5148387A Logic circuit and data processing apparatus using the same 失效
标题翻译：逻辑电路及使用其的数据处理装置
公开(公告)号：US5148387A
公开(公告)日：1992-09-15
申请号：US480674
申请日：1990-02-15
申请人： Kazuo Yano , Koichiro Ishibashi , Tetsuya Nakagawa , Katsuhiro Shimohigashi , Osamu Minato
发明人： Kazuo Yano , Koichiro Ishibashi , Tetsuya Nakagawa , Katsuhiro Shimohigashi , Osamu Minato
IPC分类号： G06F7/50 , G06F7/501
CPC分类号： G06F7/5016
摘要： A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET. An output signal related to the first, second and third input signals is generated from the output node. The output signal is, for example, a carry output signal or alternatively a majority decision logic output signal.
摘要翻译：逻辑电路包括第一，第二，第三，第四，第五和第六场效应晶体管或FET，输入节点和输出节点。第五和第六FET连接到输出节点。第一和第三FET连接到第五FET。第二和第四FET连接到第六FET。第一和第二FET连接到第一输入节点。第三和第四FET连接到第二节点。第一信号被提供给第一输入节点。向第一和第四FET的栅电极提供第二信号。具有与第二信号相反的相位的信号被提供给第二和第三FET的栅电极。第三信号被提供给第二输入节点。从第一，第二和第三信号中选择的一个信号被提供给第五FET的栅电极。具有与提供给第五FET的栅电极的信号相反的相位的信号被提供给第六FET的栅电极。从输出节点生成与第一，第二和第三输入信号有关的输出信号。输出信号例如是进位输出信号或多数决定逻辑输出信号。

10. 发明授权

US4641285A Line change-over circuit and semiconductor memory using the same 失效
标题翻译：线路切换电路和使用其的半导体存储器
公开(公告)号：US4641285A
公开(公告)日：1987-02-03
申请号：US640508
申请日：1984-08-13
申请人： Yukio Sasaki , Kotaro Nishimura , Osamu Minato
发明人： Yukio Sasaki , Kotaro Nishimura , Osamu Minato
IPC分类号： G11C8/08 , G11C29/00 , G11C29/04 , G11C11/40
CPC分类号： G11C29/78 , G11C8/08
摘要： The line change-over circuit suitable for the semiconductor memory having a redundancy memory column comprises a pair of transfer gate elements provided between a first node to which a first signal to be transmitted is supplied and a pair of transmission lines, first and second switch elements. The paired transfer gate elements are controlled on a switch in complementary manner each other according to a transfer signal. The first switch element is controlled on a switch according to the transfer signal, and the second switch element is controlled on a switch according to the first signal transmitted to one of the paired transmission lines. The first switch element turns one of the transmission lines to a fixed potential like ground potential when it is kept on, and the second switch element turns the other of the transmission lines to a fixed potential when it is kept on. The line change-over circuit in the above configuration is effective to prevent a floating state of the paired transmission lines.
摘要翻译：适用于具有冗余存储器列的半导体存储器的线转换电路包括一对传输门元件，其设置在提供有待传输的第一信号的第一节点与一对传输线之间，第一和第二开关元件。成对的传输门元件根据传输信号彼此互补地控制在开关上。第一开关元件根据传输信号被控制在开关上，并且第二开关元件根据传输到一对传输线之一的第一信号被控制在开关上。当第一开关元件保持接通时，第一开关元件将其中一个传输线转到固定电位，如接地电位，并且当第二开关元件保持接通时，第二开关元件将另一个传输线转到固定电位。上述配置中的线路切换电路有效地防止成对的传输线路的浮动状态。

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