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1. 发明授权

US5148387A Logic circuit and data processing apparatus using the same 失效
标题翻译：逻辑电路及使用其的数据处理装置
公开(公告)号：US5148387A
公开(公告)日：1992-09-15
申请号：US480674
申请日：1990-02-15
申请人： Kazuo Yano , Koichiro Ishibashi , Tetsuya Nakagawa , Katsuhiro Shimohigashi , Osamu Minato
发明人： Kazuo Yano , Koichiro Ishibashi , Tetsuya Nakagawa , Katsuhiro Shimohigashi , Osamu Minato
IPC分类号： G06F7/50 , G06F7/501
CPC分类号： G06F7/5016
摘要： A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET. An output signal related to the first, second and third input signals is generated from the output node. The output signal is, for example, a carry output signal or alternatively a majority decision logic output signal.
摘要翻译：逻辑电路包括第一，第二，第三，第四，第五和第六场效应晶体管或FET，输入节点和输出节点。第五和第六FET连接到输出节点。第一和第三FET连接到第五FET。第二和第四FET连接到第六FET。第一和第二FET连接到第一输入节点。第三和第四FET连接到第二节点。第一信号被提供给第一输入节点。向第一和第四FET的栅电极提供第二信号。具有与第二信号相反的相位的信号被提供给第二和第三FET的栅电极。第三信号被提供给第二输入节点。从第一，第二和第三信号中选择的一个信号被提供给第五FET的栅电极。具有与提供给第五FET的栅电极的信号相反的相位的信号被提供给第六FET的栅电极。从输出节点生成与第一，第二和第三输入信号有关的输出信号。输出信号例如是进位输出信号或多数决定逻辑输出信号。

2. 发明授权

US4949145A Homo-junction bipolar transistor having high base concentration and suitable for low temperature operation 失效
标题翻译：具有高碱浓度并适用于低温操作的同相双极晶体管
公开(公告)号：US4949145A
公开(公告)日：1990-08-14
申请号：US253228
申请日：1988-10-04
申请人： Kazuo Yano , Masaaki Aoki , Toshiaki Masuhara , Katsuhiro Shimohigashi
发明人： Kazuo Yano , Masaaki Aoki , Toshiaki Masuhara , Katsuhiro Shimohigashi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/36 , H01L29/66 , H01L29/732
CPC分类号： H01L29/66992 , H01L27/0623 , H01L29/36
摘要： In a homo-junction bipolar transistor suitable for a low temperature operation below 200.degree.K. (particularly below 77 K), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3. The impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.
摘要翻译：在适用于低于200°K（特别是低于77K）的低温操作的同相双极晶体管中，本征基区的杂质浓度的最大值设定为至少1×1018 / cm3。发射极区域的杂质浓度设定为比该最大值低的值。因此，可以降低基极电阻并且可以进行高速运行。此外，在本征基极区域中产生带隙变窄，并且可以将低温操作中的共发射极电流增益保持在足够的值。当这种同相双极晶体管与半导体衬底表面上的互补绝缘栅场效应晶体管一起形成时，即使在低温操作中也可以获得能够进行高速运行的Bi-CMOS器件。

3. 发明授权

US5107141A BiCMOS logic circuit using 0.5 micron technology and having an operating potential difference of less than 4 volts 失效
标题翻译： BiCMOS逻辑电路采用0.5微米技术，工作电位差小于4伏特
公开(公告)号：US5107141A
公开(公告)日：1992-04-21
申请号：US604454
申请日：1990-10-29
申请人： Kazuo Yano , Mitsuru Hiraki , Hisayuki Higuchi , Suguru Tachibana , Makoto Suzuki , Katsuhiro Shimohigashi
发明人： Kazuo Yano , Mitsuru Hiraki , Hisayuki Higuchi , Suguru Tachibana , Makoto Suzuki , Katsuhiro Shimohigashi
IPC分类号： H03K19/00 , H03K19/013 , H03K19/0944
CPC分类号： H03K19/0013 , H03K19/0136 , H03K19/09448
摘要： An output circuit portion of a BiCMOS logic circuit adapted to operating on a low voltage has an npn transistor Q5 connected between the power source Vcc and an output N6, and has an npn transistor Q6 connected between the output N6 and ground potential GND. The base of the npn transistor Q5 is driven by the drain output of p-channel MOSFETs MP3, MP4, and the base of the npn transistor Q6 is driven by the drain output of p-channel MOSFET QP5. When the power source voltage Vcc drops, the voltage applied between the drain and the source of MOSFET MP5 becomes small by the effect of V.sub.BE of the transistor Q6, but the drain current of the MOSFET MP5 changes little. Therefore, the BiCMOS circuit operates at high speeds (see FIG. 1) even when the power source voltage drops.
摘要翻译：适用于低电压工作的BiCMOS逻辑电路的输出电路部分具有连接在电源Vcc和输出N6之间的npn晶体管Q5，并具有连接在输出N6和地电位GND之间的npn晶体管Q6。 npn晶体管Q5的基极由p沟道MOSFET MP3，MP4的漏极输出驱动，npn晶体管Q6的基极由p沟道MOSFET QP5的漏极输出驱动。当电源电压Vcc下降时，通过晶体管Q6的VBE的影响，施加在MOSFET MP5的漏极和源极之间的电压变小，但MOSFET MP5的漏极电流变化较小。因此，即使当电源电压下降时，BiCMOS电路也以高速工作（参见图1）。

4. 发明授权

US5041892A Homo-junction bipolar transistor having high base concentration and suitable for low temperature operation 失效
标题翻译：具有高碱浓度并适用于低温操作的同相双极晶体管
公开(公告)号：US5041892A
公开(公告)日：1991-08-20
申请号：US522826
申请日：1990-05-14
申请人： Kazuo Yano , Masaaki Aoki , Toshiaki Masuhara , Katsuhiro Shimohigashi
发明人： Kazuo Yano , Masaaki Aoki , Toshiaki Masuhara , Katsuhiro Shimohigashi
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/36 , H01L29/66 , H01L29/732
CPC分类号： H01L29/66992 , H01L27/0623 , H01L29/36
摘要： In a homo-junction bipolar transistor suitable for a low temperature operation below 200 K. (particularly below 77 K.), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3 and the impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and a high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.

5. 发明授权

US06782499B2 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium 失效
标题翻译：半导体集成电路器件，该器件的制造方法以及计算机可读介质
公开(公告)号：US06782499B2
公开(公告)日：2004-08-24
申请号：US10285573
申请日：2002-11-01
申请人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
发明人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
IPC分类号： G01R3128
CPC分类号： G11C29/028 , G11C15/00 , G11C29/50 , G11C29/50012 , G11C2029/0403
摘要： A semiconductor integrated circuit device supplied as an IP (Intellectual Property), etc., a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing, more particularly to a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.
摘要翻译：一种半导体集成电路器件，即使在制造工艺条件变化时也保证写入和读取内置存储器的特性。半导体集成电路装置具有高速缓冲存储器，其包括由图案发生器，图案比较器和输出寄存器构成的BIST电路; 由寄存器控制信号和寄存器写入信号控制的寄存器; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。改变启用读出放大器的定时，并且通过BIST电路在定时测量存储器，由此决定最佳定时。

6. 发明授权

US06496952B1 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium 有权
标题翻译：半导体集成电路器件，该器件的制造方法以及计算机可读介质
公开(公告)号：US06496952B1
公开(公告)日：2002-12-17
申请号：US09399330
申请日：1999-09-20
申请人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
发明人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
IPC分类号： G01R3128
CPC分类号： G11C29/028 , G11C15/00 , G11C29/50 , G11C29/50012 , G11C2029/0403
摘要： A semiconductor integrated circuit device, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing are disclosed. More particularly, a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied is obtained. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by the BIST, thereby deciding the optimal timing.
摘要翻译：公开了一种半导体集成电路器件，该器件的制造方法以及用于存储用于确定用于设计的器件中构建的延迟电路的数量的处理过程的介质。更具体地说，即使在制造工艺条件变化的情况下，也能够确保写入和读出内置存储器的特性的半导体集成电路器件。半导体集成电路装置具有高速缓冲存储器，其包括由图案发生器，图案比较器和输出寄存器构成的BIST电路; 由寄存器控制信号和寄存器写入信号控制的寄存器; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。改变启用读出放大器的定时，并通过BIST测量存储器，从而确定最佳定时。

7. 发明授权

US07406643B2 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium 失效
标题翻译：半导体集成电路器件，该器件的制造方法以及计算机可读介质
公开(公告)号：US07406643B2
公开(公告)日：2008-07-29
申请号：US10860051
申请日：2004-06-04
申请人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
发明人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
IPC分类号： G01R31/28 , G11C7/00
CPC分类号： G11C29/028 , G11C15/00 , G11C29/50 , G11C29/50012 , G11C2029/0403
摘要： A semiconductor integrated circuit device which guarantees the characteristics of writing to and reading from the built-in memory even when the manufacturing process conditions are varied, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, an output register, a register controlled by a register control a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.
摘要翻译：一种半导体集成电路器件，即使在制造工艺条件变化时也保证写入和读取内部存储器的特性，制造器件的方法以及用于存储用于确定延迟次数的处理过程的介质电路内置在用于设计的设备中。半导体集成电路器件具有高速缓冲存储器，其包括由模式发生器，模式比较器，输出寄存器，由寄存器控制的寄存器控制寄存器写入信号组成的BIST电路; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。改变启用读出放大器的定时，并且通过BIST电路在定时测量存储器，由此决定最佳定时。

8. 发明申请

US20110169070A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110169070A1
公开(公告)日：2011-07-14
申请号：US13072211
申请日：2011-03-25
申请人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
发明人： Taro Osabe , Tomoyuki Ishii , Kazuo Yano , Takashi Kobayashi
IPC分类号： H01L27/088
CPC分类号： H01L27/11521 , B82Y10/00 , G11C16/0433 , G11C16/0458 , G11C16/0483 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C2216/06 , H01L27/115 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.
摘要翻译：为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过细胞水平。

9. 发明申请

US20110099054A1 HUMAN BEHAVIOR ANALYSIS SYSTEM 审中-公开
标题翻译：人类行为分析系统
公开(公告)号：US20110099054A1
公开(公告)日：2011-04-28
申请号：US12993551
申请日：2009-05-26
申请人： Norihiko Moriwaki , Kazuo Yano , Nobuo Sato , Satomi Tsuji , Koji Ara
发明人： Norihiko Moriwaki , Kazuo Yano , Nobuo Sato , Satomi Tsuji , Koji Ara
IPC分类号： G06Q10/00
CPC分类号： G06Q10/06 , G06Q10/063 , G06Q10/06395
摘要： In an organization dynamics analysis service using a sensor, organization dynamics information is understandably provided to a lot of members on a customer side without receiving private information such as an individual name from the customer. Therefore, a sensor data associated with an ID is received from the customer site, and organization analysis is performed on a service provider side, and then, an organization analysis data based on the ID is fed back to the customer site. When the customer browses the organization analysis data, the ID is converted into the private information in a service gateway installed on the customer site in accordance with a conversion table for correspondence of the ID previously specified on the customer side and the private information (individual name), and is shown to the customer as the understandable information.
摘要翻译：在使用传感器的组织动态分析服务中，可以将客户端的许多成员可理解地提供组织动态信息，而无需接收客户的个人信息等私人信息。因此，从客户站点接收与ID相关联的传感器数据，并且在服务提供方进行组织分析，然后将基于ID的组织分析数据反馈给客户站点。当客户浏览组织分析数据时，根据客户端先前指定的ID的对应关系的转换表和私人信息（个人名称）将ID转换成安装在客户站点上的服务网关中的私人信息），并向客户显示为可理解的信息。

10. 发明申请

US20110070909A1 Method of communication and base station 有权
公开(公告)号：US20110070909A1
公开(公告)日：2011-03-24
申请号：US12926449
申请日：2010-11-18
申请人： Masayuki Miyazaki , Minoru Oogushi , Kazuo Yano
发明人： Masayuki Miyazaki , Minoru Oogushi , Kazuo Yano
IPC分类号： H04B7/00
CPC分类号： H04W52/287 , H04W52/0235 , Y02D70/142
摘要： There are provided a method of communication which can reliably transmit information from a base station to a wireless terminal in a system which can reduce power consumption by intermittent operation in which the wireless terminal repeats operating state and suspended state by power on and off and the base station used for the method. The method includes the steps of storing base station information such as a command or data supplied to the wireless terminal in the base station, transferring the wireless terminal from the suspended state to the operating state to transmit information from the sensor to the base station, coupling the base station information stored in the base station to a response signal to transmit it to the wireless terminal in the operating state for transmitting the sensor information, and returning the wireless terminal to the suspended state after completing the transmission of the base station information and sensor information.

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