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1. 发明申请

US20130198254A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 有权
公开(公告)号：US20130198254A1
公开(公告)日：2013-08-01
申请号：US13801356
申请日：2013-03-13
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F17/10
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

2. 发明授权

US08396915B2 Processor for performing multiply-add operations on packed data 失效
公开(公告)号：US08396915B2
公开(公告)日：2013-03-12
申请号：US13603370
申请日：2012-09-04
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

3. 发明申请

US20130091190A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
公开(公告)号：US20130091190A1
公开(公告)日：2013-04-11
申请号：US13633086
申请日：2012-10-01
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/60
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

4. 发明申请

US20130219151A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
公开(公告)号：US20130219151A1
公开(公告)日：2013-08-22
申请号：US13801335
申请日：2013-03-13
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F9/30
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

5. 发明授权

US08495123B2 Processor for performing multiply-add operations on packed data 失效
标题翻译：用于对打包数据执行加法运算的处理器
公开(公告)号：US08495123B2
公开(公告)日：2013-07-23
申请号：US13633086
申请日：2012-10-01
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

6. 发明授权

US08626814B2 Method and apparatus for performing multiply-add operations on packed data 失效
标题翻译：对打包数据执行多重加法运算的方法和装置
公开(公告)号：US08626814B2
公开(公告)日：2014-01-07
申请号：US13175373
申请日：2011-07-01
申请人： Alexander Peleg , Milland Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Milland Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

7. 发明授权

US5642306A Method and apparatus for a single instruction multiple data early-out zero-skip multiplier 失效
标题翻译：单指令多数据提前零跳过乘数的方法和装置
公开(公告)号：US5642306A
公开(公告)日：1997-06-24
申请号：US645633
申请日：1996-05-15
申请人： Larry M. Mennemeier , Wolf C. Witt
发明人： Larry M. Mennemeier , Wolf C. Witt
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/523 , G06F2207/3828
摘要： A method and apparatus for multiple parallel multiplications of multiple packed data using a single multiplier is provided. Given multiple packed data as multiplicand blocks and as multiplier blocks, an early-out zero-skip feature examines a multiplicand block to be multiplied to determine if the multiplicand block consists of all zeros. If the multiplicand block consists of all zeros, then the corresponding multiplication is skipped. The early-out zero skip multiplier also examines the most significant bits of a multiplier block to be multiplied to determine if the most significant bits consist of all zeros. If the most significant bits of the multiplier block to be multiplied consist of all zeros, then the multiplicand block is multiplied with only the least significant bits of the corresponding multiplier block. Otherwise, if the most significant bits of the multiplier block consist of both zeros and ones, then the corresponding multiplicand block is multiplied with the entire multiplier block.
摘要翻译：提供了使用单个乘法器对多个打包数据进行多次并行乘法的方法和装置。给定多个打包数据作为被乘数块和乘数块，早期的零跳跃特征检查要乘以的被乘数块以确定被乘数块是否由全零组成。如果被乘数块由全零组成，则跳过相应的乘法。早期的零跳过乘数还检查要乘以的乘法器块的最高有效位，以确定最高有效位是否由全零组成。如果要乘法乘法器块的最高有效位由全零组成，则被乘数块仅与相应乘法器块的最低有效位相乘。否则，如果乘法器块的最高有效位由零和1组成，则相应的被乘数块与整个乘法器块相乘。

8. 发明授权

US06275840B1 Fast overflow detection in decoded bit-vector addition 有权
标题翻译：解码位向量加法中的快速溢出检测
公开(公告)号：US06275840B1
公开(公告)日：2001-08-14
申请号：US09209093
申请日：1998-12-10
申请人： Umair A. Khan , Wolf C. Witt
发明人： Umair A. Khan , Wolf C. Witt
IPC分类号： G06F752
CPC分类号： G06F7/4991 , G06F7/505
摘要： A method for detecting overflow in an add operation on first and second decoded bit-vectors is provided, the method including generating a one-ahead vector using the first decoded bit-vector. The method also includes selecting an overflow bit from bits of the one-ahead vector using the second decoded bit-vector.
摘要翻译：提供一种用于检测第一和第二解码比特向量的加法运算中的溢出的方法，所述方法包括使用第一解码比特向量生成一向前向量。该方法还包括使用第二解码比特向量从一前向量的比特中选择溢出比特。

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