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1. 发明授权

US06429692B1 High speed data sampling with reduced metastability 有权
标题翻译：具有降低亚稳态的高速数据采样
公开(公告)号：US06429692B1
公开(公告)日：2002-08-06
申请号：US09885243
申请日：2001-06-19
申请人： Edwin Chan , Kochung Lee , Ji Zhao
发明人： Edwin Chan , Kochung Lee , Ji Zhao
IPC分类号： H03K19094
CPC分类号： H03K3/356043 , H03K3/0375
摘要： A data sampling system, including a data tracking circuit and a data latching circuit, that reduces the likelihood of metastability that arises through competition of the two circuits, where data sampling occurs in a transition time interval. A combined latching and weakened tracking circuit is provided in which the tracking operation cannot change an output signal from the latching operation after the latch resolves a valid logical state.
摘要翻译：一种包括数据跟踪电路和数据锁存电路的数据采样系统，其通过两个电路的竞争降低产生亚稳态的可能性，其中在转换时间间隔内进行数据采样。提供组合的锁存和弱化跟踪电路，其中跟踪操作在锁存器解除有效逻辑状态之后不能改变来自锁存操作的输出信号。

2. 发明授权

US06614291B1 Low voltage, high speed CMOS CML latch and MUX devices 有权
标题翻译：低电压，高速CMOS CML锁存器和MUX器件
公开(公告)号：US06614291B1
公开(公告)日：2003-09-02
申请号：US09881950
申请日：2001-06-15
申请人： Ji Zhao , Kochung Lee , Edwin Chan
发明人： Ji Zhao , Kochung Lee , Edwin Chan
IPC分类号： H03K1762
CPC分类号： H03K3/356043 , H03K3/012 , H03K17/04106 , H03K17/693 , H03K2217/0036
摘要： A signal multiplexer system and a signal latch system for low voltage (Vdd≈1.2 volts) and high speed transitions between states. A dc signal isolation circuit, inserted between a clock signal circuit and a signal input/output circuit, allows use of a two-transistor-layer vertical structure that provides adequate headroom voltage (about 0.3-0.4 volts, or larger) for high speed transistor response.
摘要翻译：用于低电压（Vdd≈1.2伏）和状态之间的高速转换的信号复用器系统和信号锁存系统。插入在时钟信号电路和信号输入/输出电路之间的直流信号隔离电路允许使用双晶体管层垂直结构，为高速晶体管提供足够的净空电压（约0.3-0.4伏或更大）响应。

3. 发明申请

US20110150055A1 Active Auxiliary Channel Buffering 有权
标题翻译：主动辅助通道缓冲
公开(公告)号：US20110150055A1
公开(公告)日：2011-06-23
申请号：US12645240
申请日：2009-12-22
申请人： Ming Qu , Zhengyu Yuan , Kochung Lee
发明人： Ming Qu , Zhengyu Yuan , Kochung Lee
IPC分类号： H04B1/38
CPC分类号： G09G5/006 , G09G2330/021 , G09G2350/00 , G09G2370/045 , G09G2370/10 , H04L65/4023 , H04L65/4092 , H04L67/34
摘要： A system and a method for communicating configuration data between a source device and a sink are described. An active buffer receives data from an auxiliary communication channel which communicates data between the source device and the sink device. The active buffer modifies data received from the auxiliary communication channel. For example, the active buffer amplifies the received data or electrically reshapes the received data. The modified data is then transmitted from the active buffer to a destination device. In one embodiment, the auxiliary communication channel is bi-directional and upon receiving data from a first device, the active buffer is modified to permit uni-directional transmission of data from the first device to a second device.
摘要翻译：描述用于在源设备和宿之间传送配置数据的系统和方法。主动缓冲器从辅助通信信道接收数据，该辅助通信信道在源设备和宿设备之间传送数据。主动缓冲器修改从辅助通信信道接收到的数据。例如，有源缓冲器放大所接收的数据或电接收数据。然后将修改的数据从活动缓冲器发送到目的地设备。在一个实施例中，辅助通信信道是双向的，并且在从第一设备接收数据时，主动缓冲器被修改以允许将数据从第一设备单向传输到第二设备。

4. 发明申请

US20140003480A1 On Die Jitter Tolerance Test 有权
标题翻译：关于死机容忍测试
公开(公告)号：US20140003480A1
公开(公告)日：2014-01-02
申请号：US13538930
申请日：2012-06-29
申请人： Ming Qu , Yuanping Chen , Yuntao Zhu , Quan Yu , Kochung Lee
发明人： Ming Qu , Yuanping Chen , Yuntao Zhu , Quan Yu , Kochung Lee
IPC分类号： H04B17/00
CPC分类号： H03L7/087 , G01R29/26 , H03L7/0807 , H03L7/081 , H03L7/0998 , H04B17/104 , H04L1/205 , H04L1/243 , H04L7/033
摘要： A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.
摘要翻译：公开了一种用于执行裸片抖动容限测试的系统和方法。基于输入信号产生一组时钟。该组时钟包括基于输入信号的数据切换沿的同相信号。此外，该组时钟包括偏移180度的反相时钟相位和一对相位偏移一定数量度θ的时钟。基于反相时钟和两个相移时钟对数据输入进行采样。可以基于反相时钟和两个相移时钟中的每一个是否以各种θ值从输入信号中采样正确的数据来确定输入信号的开眼。

5. 发明授权

US07196551B2 Current mode logic buffer 有权
标题翻译：电流模式逻辑缓冲器
公开(公告)号：US07196551B2
公开(公告)日：2007-03-27
申请号：US10856100
申请日：2004-05-28
申请人： Kochung Lee
发明人： Kochung Lee
IPC分类号： H03K19/20
CPC分类号： H03K19/018528
摘要： Systems and methods provide current mode logic buffers and interface circuits. As an example, in accordance with an embodiment of the present invention, a CML buffer is disclosed that receives and/or provides multiple signal pairs having different common mode voltages to operate over a wider common mode voltage range.
摘要翻译：系统和方法提供电流模式逻辑缓冲器和接口电路。作为示例，根据本发明的实施例，公开了一种CML缓冲器，其接收和/或提供具有不同共模电压的多个信号对以在更宽的共模电压范围内工作。

6. 发明授权

US08610479B2 On die low power high accuracy reference clock generation 有权
标题翻译：低功耗高精度基准时钟生成
公开(公告)号：US08610479B2
公开(公告)日：2013-12-17
申请号：US13276269
申请日：2011-10-18
申请人： Kochung Lee , Quan Yu , Yuntao Zhu , Lei Xie , Ming Qu
发明人： Kochung Lee , Quan Yu , Yuntao Zhu , Lei Xie , Ming Qu
IPC分类号： G06F1/04
CPC分类号： H03L7/22
摘要： A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.
摘要翻译：公开了一种用于在芯片参考时钟上产生高精度和低功耗的系统和方法。在芯片上产生LC时钟，分频器将LC时钟频率降低到目标参考频率。在未知的初始频率的芯片上产生RCO时钟。比较RCO时钟和目标参考时钟，确定在哪个方向上调整RCO时钟的频率以更接近目标参考频率。发送信号，导致RCO电路中的电流源或电容器被修改。因此，调整RCO时钟频率。 RCO电路重复调整，直到RCO时钟频率足够准确。 LC时钟被禁用，以节省在生成LC时钟时消耗的功率。

7. 发明申请

US20130093466A1 ON DIE LOW POWER HIGH ACCURACY REFERENCE CLOCK GENERATION 有权
标题翻译： ON DIE低功率高精度参考时钟产生
公开(公告)号：US20130093466A1
公开(公告)日：2013-04-18
申请号：US13276269
申请日：2011-10-18
申请人： Kochung Lee , Quan Yu , Yuntao Zhu , Lei Xie , Ming Qu
发明人： Kochung Lee , Quan Yu , Yuntao Zhu , Lei Xie , Ming Qu
IPC分类号： H03D13/00
CPC分类号： H03L7/22
摘要： A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.
摘要翻译：公开了一种用于在芯片参考时钟上产生高精度和低功耗的系统和方法。在芯片上产生LC时钟，分频器将LC时钟频率降低到目标参考频率。在未知的初始频率的芯片上产生RCO时钟。比较RCO时钟和目标参考时钟，确定在哪个方向上调整RCO时钟的频率以更接近目标参考频率。发送信号，导致RCO电路中的电流源或电容器被修改。因此，调整RCO时钟频率。 RCO电路重复调整，直到RCO时钟频率足够准确。 LC时钟被禁用，以节省在生成LC时钟时消耗的功率。

8. 发明申请

US20110149796A1 DisplayPort Auxiliary Channel Active Buffer with Auxiliary Channel/Display Data Channel Combiner for Fast Auxiliary Channel 有权
标题翻译： DisplayPort辅助通道主动缓冲器，辅助通道/显示数据通道组合器，用于快速辅助通道
公开(公告)号：US20110149796A1
公开(公告)日：2011-06-23
申请号：US12643759
申请日：2009-12-21
申请人： Ming Qu , Zhengyu Yuan , Kochung Lee
发明人： Ming Qu , Zhengyu Yuan , Kochung Lee
IPC分类号： H04L12/28
CPC分类号： G06F3/14 , G09G5/003 , G09G5/363 , G09G2370/047 , G09G2370/12 , H04L43/16
摘要： A system and a method for exchanging communication data between devices using a bi-directional communication channel are disclosed. A combiner is coupled to a source device via first bi-directional configuration channel and to a sink device via a second bi-directional configuration channel. Upon receiving data from the first bi-directional configuration channel and not receiving data from the second bi-directional configuration channel, the combiner transmits the received data to the sink device using the second bi-directional configuration channel and prevents data transmission from the sink device to the source device using the second bi-directional configuration channel. Similarly, upon receiving data from the second bi-directional configuration channel and not receiving from the first bi-directional configuration channel, the combiner prevents data transmission from the source device to the sink device and transmits the received data to the source device using the first bi-directional configuration channel.
摘要翻译：公开了一种使用双向通信信道在设备之间交换通信数据的系统和方法。组合器经由第一双向配置信道耦合到源设备，并经由第二双向配置信道耦合到宿设备。在从第一双向配置信道接收数据并且没有从第二双向配置信道接收数据时，组合器使用第二双向配置信道将接收的数据发送到宿设备，并且防止从宿设备的数据传输使用第二双向配置信道到源设备。类似地，当从第二双向配置信道接收到数据并且没有从第一双向配置信道接收时，组合器防止从源设备到宿设备的数据传输，并且使用第一双向配置信道将接收到的数据发送到源设备双向配置通道。

9. 发明授权

US08982932B2 Active auxiliary channel buffering 有权
标题翻译：主动辅助通道缓冲
公开(公告)号：US08982932B2
公开(公告)日：2015-03-17
申请号：US12645240
申请日：2009-12-22
申请人： Ming Qu , Zhengyu Yuan , Kochung Lee
发明人： Ming Qu , Zhengyu Yuan , Kochung Lee
IPC分类号： H04B1/38 , H04L5/16 , G09G5/00 , H04L29/06 , H04L29/08
CPC分类号： G09G5/006 , G09G2330/021 , G09G2350/00 , G09G2370/045 , G09G2370/10 , H04L65/4023 , H04L65/4092 , H04L67/34
摘要： A system and a method for communicating configuration data between a source device and a sink are described. An active buffer receives data from an auxiliary communication channel which communicates data between the source device and the sink device. The active buffer modifies data received from the auxiliary communication channel. For example, the active buffer amplifies the received data or electrically reshapes the received data. The modified data is then transmitted from the active buffer to a destination device. In one embodiment, the auxiliary communication channel is bi-directional and upon receiving data from a first device, the active buffer is modified to permit uni-directional transmission of data from the first device to a second device.
摘要翻译：描述用于在源设备和宿之间传送配置数据的系统和方法。主动缓冲器从辅助通信信道接收数据，该辅助通信信道在源设备和宿设备之间传送数据。主动缓冲器修改从辅助通信信道接收到的数据。例如，有源缓冲器放大所接收的数据或电接收数据。然后将修改的数据从活动缓冲器发送到目的地设备。在一个实施例中，辅助通信信道是双向的，并且在从第一设备接收数据时，主动缓冲器被修改以允许将数据从第一设备单向传输到第二设备。

10. 发明授权

US08923375B2 On die jitter tolerance test 有权
标题翻译：裸片抖动容限测试
公开(公告)号：US08923375B2
公开(公告)日：2014-12-30
申请号：US13538930
申请日：2012-06-29
申请人： Ming Qu , Yuanping Chen , Yuntao Zhu , Quan Yu , Kochung Lee
发明人： Ming Qu , Yuanping Chen , Yuntao Zhu , Quan Yu , Kochung Lee
IPC分类号： H04B17/00
CPC分类号： H03L7/087 , G01R29/26 , H03L7/0807 , H03L7/081 , H03L7/0998 , H04B17/104 , H04L1/205 , H04L1/243 , H04L7/033
摘要： A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.
摘要翻译：公开了一种用于执行裸片抖动容限测试的系统和方法。基于输入信号产生一组时钟。该组时钟包括基于输入信号的数据切换沿的同相信号。此外，该组时钟包括一个偏移180度的反相时钟相位和一对相位正负偏移一定数量的时钟。基于反相时钟和两个相移时钟对数据输入进行采样。输入信号的开眼可以基于每个反相时钟和两个相移时钟从各种输入信号中的输入信号中得到正确的数据来确定; 价值观。

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