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1. 发明授权

US5266516A Method for making electrical contact through an opening of one micron or less for CMOS technology 失效
标题翻译： CMOS技术通过一微米或更小的开口进行电接触的方法
公开(公告)号：US5266516A
公开(公告)日：1993-11-30
申请号：US815745
申请日：1992-01-02
申请人： Bernard W. K. Ho
发明人： Bernard W. K. Ho
IPC分类号： H01L21/768 , H01L23/532 , H01L21/70
CPC分类号： H01L21/7688 , H01L21/76877 , H01L23/532 , H01L2924/0002 , Y10S148/051
摘要： A new method to produce a contact or via opening and filled metallurgy for integrated circuits. An insulating layer structure is formed over semiconductor device structures. A resist mask with substantially vertical sided openings is formed in the mask over the insulating layer and above the device elements to be electrically contacted. These device elements can be, for example source/drain regions in the semiconductor substrate, a metallurgy layer interconnecting other device element and the like. The exposed insulating layer is isotropically etched to a depth of between about 500 to 850 Angstroms to form a break in the vertical sided opening under construction. The exposed insulating layer is anisotropically etched to complete the construction of the substantially vertical sided openings through the insulating layer to a device element to be electrically contacted. A metal layer is sputter deposited over the exposed surfaces including the device elements at the bottom of the vertical sided openings, while substantially not depositing the metal upon the vertical sides of the openings. The resist mask and the metal thereover is removed by etching with the break being the attacking point of the resist etching fluid. A next level metallurgy is deposited over the exposed surfaces including the metal remaining in the vertical sided openings to form the next metallurgy level and to complete contact.
摘要翻译：一种用于集成电路产生接触或通过开孔和填充冶金的新方法。在半导体器件结构上形成绝缘层结构。在掩模上形成具有基本上垂直的侧面开口的抗蚀剂掩模，并且在电气接触的器件元件之上。这些器件元件可以是例如半导体衬底中的源极/漏极区域，与其它器件元件等互连的冶金层。暴露的绝缘层被各向同性蚀刻到约500至850埃之间的深度，以在构造的垂直侧面开口中形成断裂。暴露的绝缘层被各向异性地蚀刻以完成通过绝缘层到被电接触的器件元件的基本垂直的侧面开口的结构。金属层溅射沉积在暴露的表面上，包括位于垂直侧面开口底部的器件元件，同时基本上不将金属沉积在开口的垂直侧上。通过蚀刻去除抗蚀剂掩模和其上的金属，其中断裂是抗蚀剂蚀刻流体的攻击点。下一级冶金沉积在暴露的表面上，包括留在垂直侧面开口中的金属，以形成下一个冶金级别并完成接触。

2. 发明授权

US5225357A Low P+ contact resistance formation by double implant 失效
标题翻译：通过双重植入物形成低P +接触电阻
公开(公告)号：US5225357A
公开(公告)日：1993-07-06
申请号：US815515
申请日：1992-01-02
申请人： Bernard W. K. Ho
发明人： Bernard W. K. Ho
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/2652
摘要： The method of manufacture of a PMOS integrated circuit having a feature size in the order of one micron or less is done by providing, on a silicon substrate, a pattern of silicon gate electrodes over a gate dielectric. Implanting of BF.sub.2 + ions and B11+ ions sequentially by using the pattern as a mask. The structure is annealed at more than about 850.degree. C. to complete the PMOS integrated circuit. This method results in lower contact resistance to the P+ regions and lower sheet resistance for higher speed CMOS integrated circuits at minimal increase of manufacturing cost.
摘要翻译：通过在硅衬底上提供栅极电介质上的硅栅电极的图案来制造具有1微米或更小的特征尺寸的PMOS集成电路的制造方法。通过使用图案作为掩模，顺序地注入BF2 +离子和B11 +离子。该结构在超过约850℃退火以完成PMOS集成电路。该方法导致较低的P +区域的接触电阻和较低的CMOS集成电路的薄层电阻，并以最小的制造成本增加。

3. 发明授权

US4892844A Making a low resistance three layered contact for silicon devices 失效
标题翻译：为硅器件制造低电阻三层接触
公开(公告)号：US4892844A
公开(公告)日：1990-01-09
申请号：US285188
申请日：1988-12-16
申请人： Robin W. Cheung , Bernard W. K. Ho , Hsiang-Wen Chen , Hugo W. K. Chan
发明人： Robin W. Cheung , Bernard W. K. Ho , Hsiang-Wen Chen , Hugo W. K. Chan
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3205 , H01L23/52 , H01L23/522 , H01L23/532 , H01L29/43
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S148/019
摘要： A three-layer metal contact including aluminum is provided for silicon-based semiconductor devices to minimize the effects of formation of silicon precipitates in the aluminum layer and low contact junction leakage. The metal contact comprises a first layer of a refractory metal silicide formed on a silicon surface, an intermediate layer of aluminum formed on the refractory metal silicide and a top layer of a refractory metal silicide formed on the layer of aluminum. Where contact is made to polysilicon layers forming high resistance load resistors, the metal contact of the invention prevents reduction in resistance resulting from the interdiffusion of silicon and aluminum.

4. 发明授权

US4796081A Low resistance metal contact for silicon devices 失效
标题翻译：硅器件的低电阻金属接触
公开(公告)号：US4796081A
公开(公告)日：1989-01-03
申请号：US858994
申请日：1986-05-02
申请人： Robin W. Cheung , Bernard W. K. Ho , Hsiang-Wen Chen , Hugo W. K. Chan
发明人： Robin W. Cheung , Bernard W. K. Ho , Hsiang-Wen Chen , Hugo W. K. Chan
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3205 , H01L23/52 , H01L23/522 , H01L23/532 , H01L29/43 , H01L23/48
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S148/019
摘要： A three-layer metal contact including aluminum is provided for silicon-based semiconductor devices to minimize the effects of formation of silicon precipitates in the aluminum layer and low contact junction leakage. The metal contact comprises a first layer of a refractory metal silicide formed on a silicon surface, an intermediate layer of aluminum formed on the refractory metal silicide and a top layer of a refractory metal silicide formed on the layer of aluminum. Where contact is made to polysilicon layers forming high resistance load resistors, the metal contact of the invention prevents reduction in resistance resulting from the interdiffusion of silicon and aluminum.
摘要翻译：为硅基半导体器件提供包括铝的三层金属接触，以最大限度地减少铝层中硅沉淀物的形成和低接触结漏电的影响。金属接触包括形成在硅表面上的难熔金属硅化物的第一层，形成在难熔金属硅化物上的铝的中间层和形成在铝层上的难熔金属硅化物的顶层。当与形成高电阻负载电阻器的多晶硅层接触时，本发明的金属接触防止由于硅和铝的相互扩散而导致的电阻降低。

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