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    • 1. 发明授权
    • Peltier module
    • 珀耳帖模块
    • US5841064A
    • 1998-11-24
    • US776186
    • 1997-01-24
    • Nobuteru MaekawaKatsuyoshi ShimodaTeruaki KomatsuShinya MuraseHiroaki OkadaHiroyuki Inoue
    • Nobuteru MaekawaKatsuyoshi ShimodaTeruaki KomatsuShinya MuraseHiroaki OkadaHiroyuki Inoue
    • F25B21/02H01L35/32H01L35/02H01L35/08
    • H01L35/32
    • A Peltier effect module comprising a plurality of Peltier effect elements arranged in parallel between a pair of substrates where the Peltier effect elements are connected to connection electrodes disposed on the substrates. The array of Peltier effect elements is sealed off by a hollow seal frame surrounding the Peltier effect element array with a seal formed by a bond between both end edges of the seal frame and the substrates. Because the perimeter around the Peltier effect elements is sealed using a seal frame metalically bonded at both ends to the substrates, resistance to moisture penetration is largely determined by the material from which the seal frame is made. Therefore, by appropriately selecting the seal frame materials, the Peltier effect module can be reliably protected for a long period of time against moisture penetration.
    • PCT No.PCT / JP96 / 01421 Sec。 371日期1997年1月24日 102(e)日期1997年1月24日PCT提交1996年5月27日PCT公布。 WO96 / 37918 PCT公开号 日期:1996年11月28日帕尔帖效应模块包括平行布置在一对基板之间的多个珀耳帖效应元件,其中帕尔帖效应元件连接到设置在基板上的连接电极。 Peltier效应元件的阵列由围绕珀尔帖效应元件阵列的中空密封框架密封,密封框架和基板的两端边缘之间的接合形成密封。 由于珀耳帖效应元件周围的周边是使用两端金属结合到基板上的密封框进行密封的,所以耐水分渗透的程度很大程度上取决于制作密封框架的材料。 因此,通过适当选择密封框架材料,可以长时间可靠地保护珀尔帖效应模块以防止水分渗透。
    • 2. 发明授权
    • Thermoelectric module with interarray bridges
    • 带电桥的热电模块
    • US06400013B1
    • 2002-06-04
    • US09709577
    • 2000-11-13
    • Michimasa TsuzakiNobuteru MaekawaNarimasa IwamotoJunji ImaiHiroaki OkadaTeruaki KomatsuShinya MuraseHiroyuki InoueMasayuki SagawaYuri Sakai
    • Michimasa TsuzakiNobuteru MaekawaNarimasa IwamotoJunji ImaiHiroaki OkadaTeruaki KomatsuShinya MuraseHiroyuki InoueMasayuki SagawaYuri Sakai
    • H01L2334
    • H01L35/325H01L35/32H01L2924/0002H01L2924/00
    • A thermoelectric module is capable of successfully reducing the heat stress for increased reliability. The module includes a plurality of thermoelectric chips of P-type and N-type arranged in a matrix between sets of first and second contacts to form a series electrical circuit. The chips are arranged to give at least three chip arrays each having a limited number of the chips. A first carrier is provided on one side of the chips to carry the first contacts and to include first bridges each integrally joining two adjacent first contacts to define first discrete couples for electrical connection of the chips in each chip array. The first carrier further includes at least two inter-array bridges which are solely responsible for electrical interconnection between the adjacent chip arrays. On the opposite side of the chips, there are formed a plurality of second bridges each integrally joining the two adjacent second contacts to give second discrete couples for electrical connection of the two adjacent chips in each of the chip arrays. Thus, the inter-array bridges are formed only on one side of the chips for interconnection of the first contacts between the adjacent chip arrays. Therefore, the heat stress applied to the end of the chip array where the two adjacent chip arrays are interconnected can be well relieved on the side of the second contacts in which the second discrete couples are kept totally isolated from each other.
    • 热电模块能够成功地降低热应力以提高可靠性。 该模块包括在第一和第二触点组之间以矩阵形式布置的多个P型和N型热电芯片,以形成串联电路。 芯片被布置成给出至少三个芯片阵列,每个芯片阵列具有有限数量的芯片。 第一载体设置在芯片的一侧以承载第一触点并且包括每个一体地连接两个相邻的第一触点的第一桥,以限定用于每个芯片阵列中的芯片的电连接的第一离散耦合。 第一载体还包括至少两个排列间桥,其单独负责相邻芯片阵列之间的电互连。 在芯片的相对侧,形成多个第二桥,每个第二桥整体地连接两个相邻的第二触点,以给出第二离散耦合,用于电连接每个芯片阵列中的两个相邻的芯片。 因此,阵列间桥仅形成在芯片的一侧,用于相邻芯片阵列之间的第一触点的互连。 因此,施加到两个相邻芯片阵列相互连接的芯片阵列的端部的热应力可以在第二接触件的一侧彼此完全隔离的第二触头侧得到很好的缓解。
    • 3. 发明授权
    • Thermoelectric module and a method of fabricating the same
    • 热电模块及其制造方法
    • US06391676B1
    • 2002-05-21
    • US09200972
    • 1998-11-30
    • Michimasa TsuzakiNobuteru MaekawaNarimasa IwamotoJunji ImaiHiroaki OkadaTeruaki KomatsuShinya MuraseHiroyuki InoueMasayuki SagawaYuri Sakai
    • Michimasa TsuzakiNobuteru MaekawaNarimasa IwamotoJunji ImaiHiroaki OkadaTeruaki KomatsuShinya MuraseHiroyuki InoueMasayuki SagawaYuri Sakai
    • H01L2100
    • H01L35/325H01L35/32H01L2924/0002H01L2924/00
    • A thermoelectric module is capable of successfully reducing the heat stress for increased reliability. The module includes a plurality of thermoelectric chips of P-type and N-type arranged in a matrix between sets of first and second contacts to form a series electrical circuit. The chips are arranged to give at least three chip arrays each having a limited number of the chips. A first carrier is provided on one side of the chips to carry the first contacts and to include first bridges each integrally joining two adjacent first contacts to define first discrete couples for electrical connection of the chips in each chip array. The first carrier further includes at least two inter-array bridges which are solely responsible for electrical interconnection between the adjacent chip arrays. On the opposite side of the chips, there are formed a plurality of second bridges each integrally joining the two adjacent second contacts to give second discrete couples for electrical connection of the two adjacent chips in each of the chip arrays. Thus, the inter-array bridges are formed only on one side of the chips for interconnection of the first contacts between the adjacent chip arrays. Therefore, the heat stress applied to the end of the chip array where the two adjacent chip arrays are interconnected can be well relieved on the side of the second contacts in which the second discrete couples are kept totally isolated from each other.
    • 热电模块能够成功地降低热应力以提高可靠性。 该模块包括在第一和第二触点组之间以矩阵形式布置的多个P型和N型热电芯片,以形成串联电路。 芯片被布置成给出至少三个芯片阵列,每个芯片阵列具有有限数量的芯片。 第一载体设置在芯片的一侧以承载第一触点并且包括每个一体地连接两个相邻的第一触点的第一桥,以限定用于每个芯片阵列中的芯片的电连接的第一离散耦合。 第一载体还包括至少两个排列间桥,其单独负责相邻芯片阵列之间的电互连。 在芯片的相对侧,形成多个第二桥,每个第二桥整体地连接两个相邻的第二触点,以给出第二离散耦合,用于电连接每个芯片阵列中的两个相邻的芯片。 因此,阵列间桥仅形成在芯片的一侧,用于相邻芯片阵列之间的第一触点的互连。 因此,施加到两个相邻芯片阵列相互连接的芯片阵列的端部的热应力可以在第二接触件的一侧彼此完全隔离的第二触头侧得到很好的缓解。
    • 4. 发明授权
    • Method of fabricating a thermoelectric module
    • 制造热电模块的方法
    • US5950067A
    • 1999-09-07
    • US973095
    • 1998-03-19
    • Nobuteru MaegawaHiroaki OkadaMichimasa TsuzakiYuri SakaiKatsuyoshi ShimodaTeruaki KomatsuShinya MuraseHiroyuki InoueMasayuki Sagawa
    • Nobuteru MaegawaHiroaki OkadaMichimasa TsuzakiYuri SakaiKatsuyoshi ShimodaTeruaki KomatsuShinya MuraseHiroyuki InoueMasayuki Sagawa
    • H01L35/32H01L35/34H01L21/324
    • H01L35/32H01L35/325H01L35/34Y10S257/93
    • A method of fabricating a thermoelectric module in which a plurality of thermoelectric chips are arranged in a matrix between first and second dielectric substrates and electrically connected in series so as to heat one of the substrates and cool the other substrate. Elongated thermoelectric bars of P-type and N-type to be cut into the chips are employed together with a first conductive plate having a plurality of first contacts arranged in a matrix pattern. Adjacent first contacts spaced along the row are interconnected by horizontal bridges. The method of the present invention comprises the steps of integrating the first conductive plate to the first substrate to support the first conductive plate thereby; placing a plurality of the bars of the P-type and N-type on the first contacts along the rows in such a manner that the P-type bars alternate with the N-type bars in a spaced relation along the column; bonding each bar on its one face to the first contacts; cutting each bar into the chips and cutting the horizontal bridges simultaneously to allocate the chips on the individual first contacts; placing a plurality of second contacts of a second substrate onto the chips to form a series electric circuit of the chips in combination with the first contacts, and bonding the second substrate supporting the second contacts to the first substrate.
    • PCT No.PCT / JP97 / 01797 Sec。 371日期:1998年3月19日 102(e)1998年3月19日PCT PCT 1997年6月3日PCT公布。 公开号WO97 / 45882 日期1997年12月4日一种制造热电模块的方法,其中多个热电芯片以矩阵形式布置在第一和第二电介质基板之间并串联电连接以加热其中一个基板并冷却另一个基板。 将要切割成芯片的P型和N型的细长热电棒与具有以矩阵图案排列的多个第一触头的第一导电板一起使用。 沿着行间隔的相邻的第一接触件通过水平桥互连。 本发明的方法包括以下步骤:将第一导电板与第一基板集成,从而支撑第一导电板; 沿着行将P型和N型的多个条放置在第一触点上,使得P型条以与柱相隔的关系与N型条交替; 将其一个面上的每个条连接到第一触点; 将每个棒切割成芯片并同时切割水平桥,以将芯片分配在单独的第一触点上; 将第二基板的多个第二触点放置在芯片上以与第一触点组合形成芯片的串联电路,以及将支撑第二触点的第二基板接合到第一基板。
    • 9. 发明授权
    • Image formation apparatus
    • 图像形成装置
    • US08750731B2
    • 2014-06-10
    • US13354865
    • 2012-01-20
    • Hiroyuki Inoue
    • Hiroyuki Inoue
    • G03G15/00
    • G03G15/50G03G15/5008G03G15/6564G03G2215/00721
    • An image formation apparatus includes an image carrier on which a developer image is to be formed, an image transfer device configured to transfer the developer image formed on the image carrier to a medium at an image transfer position, a controller configured to control drive of the image carrier and the image transfer device, a first medium feeder configured to feed the medium to the image transfer position along a medium conveyance path extending from the first medium feeder to the image transfer position, and a medium detector provided between the first medium feeder and the image transfer position in the medium conveyance path. The controller is configured to control the drive of the image carrier on the basis of a medium-detection result by the medium detector.
    • 图像形成装置包括要在其上形成显影剂图像的图像载体,被配置为将形成在图像载体上的显影剂图像转印到图像转印位置的介质的图像转印装置,被配置为控制图像载体 图像载体和图像转印装置,第一介质供给器,被配置为沿着从第一介质进料器延伸到图像转印位置的介质输送路径将介质输送到图像转印位置,以及介质检测器,设置在第一介质进料器和 介质输送路径中的图像转印位置。 控制器被配置为基于介质检测器的介质检测结果来控制图像载体的驱动。