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1. 发明申请

US20050000410A1 Manufacturing method of high resistivity silicon single crystal 有权
标题翻译：高电阻率硅单晶的制造方法
公开(公告)号：US20050000410A1
公开(公告)日：2005-01-06
申请号：US10828555
申请日：2004-04-21
申请人： Nobumitsu Takase , Hideshi Nishikawa , Makoto Ito , Kouji Sueoka , Shinsuke Sadamitsu
发明人： Nobumitsu Takase , Hideshi Nishikawa , Makoto Ito , Kouji Sueoka , Shinsuke Sadamitsu
IPC分类号： C30B15/00 , C30B29/06 , C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： C30B29/06 , C30B15/00
摘要： To suppress a fluctuation in resistivity around a target value to thereby stably manufacture high resistivity silicon single crystals having almost the same resistivity values in a manufacturing method wherein a silicon raw material is molten to manufacture a high resistivity silicon single crystal in the range of from 100 to 2000 Ω cm with a CZ method. In a case where poly-silicon produced with a Siemens method using trichlorosilane as raw material is used as the silicon raw material, an impurity concentration in the silicon raw material is selected so as to be controlled in the range of from −5 to 50 ppta method in terms of (a donor concentration—an acceptor concentration) and the selected poly-silicon is used. In a case of a MCZ method, the poly-silicon is selected in the range of from −25 to 20 ppta and the selected poly-silicon is used. Instead of the raw material, poly-silicon produced with a Siemens method using monosilane as raw material is used. Alternatively, a silicon crystal manufactured with a CZ method or a MCZ method using poly-silicon raw material is used.
摘要翻译：为了抑制围绕目标值的电阻率的波动，从而在将硅原料熔融以制造范围为100的高电阻率硅单晶的制造方法中稳定地制造具有几乎相同的电阻率值的高电阻率硅单晶到2000欧米加厘米与CZ方法。在使用以三氯硅烷为原料的西门子方法制造的多晶硅作为硅原料的情况下，选择硅原料中的杂质浓度以控制在-5〜50ppta的范围内使用（供体浓度 - 受体浓度）和选择的多晶硅的方法。在MCZ方法的情况下，多晶硅的选择范围为-25〜20ppta，使用所选择的多晶硅。使用以硅烷为原料的西门子法生产的多晶硅代替原料。或者，使用以CZ法制造的硅晶体或使用多晶硅原料的MCZ法。

2. 发明授权

US07397110B2 High resistance silicon wafer and its manufacturing method 有权
标题翻译：高电阻硅晶片及其制造方法
公开(公告)号：US07397110B2
公开(公告)日：2008-07-08
申请号：US10512405
申请日：2003-04-16
申请人： Nobumitsu Takase , Hideshi Nishikawa , Makoto Ito , Koji Sueoka , Shinsuke Sadamitsu
发明人： Nobumitsu Takase , Hideshi Nishikawa , Makoto Ito , Koji Sueoka , Shinsuke Sadamitsu
IPC分类号： H01L29/36 , H01L21/322
CPC分类号： H01L21/3225
摘要： A high-resistance silicon wafer is manufactured in which a gettering ability, mechanical strength, and economical efficiency are excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is implemented on the side of a device maker. A heat treatment for forming an oxygen precipitate nucleus is performed at 500 to 900° C. for 5 hours or more in a non-oxidizing atmosphere and a heat treatment for growing an oxygen precipitate is performed at 950 to 1050° C. for 10 hours or more on a high-oxygen and carbon-doped high-resistance silicon wafer in which resistivity is 100 Ωcm or more, an oxygen concentration is 14×1017 atoms/cm3 (ASTM F-121, 1979) or more and a carbon concentration is 0.5×1016 atoms/cm3 or more. By these heat treatments, a remaining oxygen concentration in the wafer is controlled to be 12×1017 atoms/cm3 (ASTM F-121, 1979) or less. Thus, there is provided a high-resistance, low-oxygen and high-strength silicon wafer in which resistivity is 100 Ωcm or more and an oxygen precipitate (BMD) having a size of 0.2 μm is formed so as to have high density of 1×104/cm2 or more.
摘要翻译：制造高电阻硅晶片，其中吸收能力，机械强度和经济效率优异，并且在用于形成电路的热处理中有效地防止了氧热供体的产生，该电路在设备制造商。在非氧化性气氛中，在500〜900℃下进行形成氧沉淀核的热处理5小时以上，在950〜1050℃下进行氧沉淀的热处理10小时以上，电阻率为100Ωm以上的高氧和碳掺杂高电阻硅晶片，氧浓度为14×10 17原子/ cm 3（以下） ASTM F-121,1979）或更高，碳浓度为0.5×10 16原子/ cm 3以上。通过这些热处理，将晶片中的剩余氧浓度控制为12×10 17原子/ cm 3（ASTM F-121,1979）或更小。因此，提供了电阻率为100Ωm或更大的高电阻，低氧和高强度硅晶片，并且形成具有0.2μm大小的氧沉淀物（BMD），以便具有高密度的1×10 4/4以上。

3. 发明申请

US20050253221A1 High resistance silicon wafer and method for production thereof 有权
标题翻译：高电阻硅晶片及其制造方法
公开(公告)号：US20050253221A1
公开(公告)日：2005-11-17
申请号：US10512405
申请日：2003-04-16
申请人： Nobumitsu Takase , Hideshi Nishikawa , Makoto Ito , Koji Sueoka , Shinsuke Sadamitsu
发明人： Nobumitsu Takase , Hideshi Nishikawa , Makoto Ito , Koji Sueoka , Shinsuke Sadamitsu
IPC分类号： H01L21/26 , H01L21/322 , H01L29/167 , H01L21/22
CPC分类号： H01L21/3225
摘要： A high-resistance silicon wafer is manufactured in which a gettering ability, mechanical strength, and economical efficiency are excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is implemented on the side of a device maker. A heat treatment for forming an oxygen precipitate nucleus is performed at 500 to 900° C. for 5 hours or more in a non-oxidizing atmosphere and a heat treatment for growing an oxygen precipitate is performed at 950 to 1050° C. for 10 hours or more on a high-oxygen and carbon-doped high-resistance silicon wafer in which resistivity is 100 Ωcm or more, an oxygen concentration is 14×1017 atoms/cm3 (ASTM F-121, 1979) or more and a carbon concentration is 0.5×1016 atoms/cm3 or more. By these heat treatments, a remaining oxygen concentration in the wafer is controlled to be 12×1017 atoms/cm3 (ASTM F-121, 1979) or less. Thus, there is provided a high-resistance, low-oxygen and high-strength silicon wafer in which resistivity is 100 Ωcm or more and an oxygen precipitate (BMD) having a size of 0.2 μm is formed so as to have high density of 1×104/cm2 or more.
摘要翻译：制造高电阻硅晶片，其中吸收能力，机械强度和经济效率优异，并且在用于形成电路的热处理中有效地防止了氧热供体的产生，该电路在设备制造商。在非氧化性气氛中，在500〜900℃下进行形成氧沉淀核的热处理5小时以上，在950〜1050℃下进行氧沉淀的热处理10小时以上，电阻率为100Ωm以上的高氧和碳掺杂高电阻硅晶片，氧浓度为14×10 17原子/ cm 3（以下） ASTM F-121,1979）或更高，碳浓度为0.5×10 16原子/ cm 3以上。通过这些热处理，将晶片中的剩余氧浓度控制为12×10 17原子/ cm 3（ASTM F-121,1979）或更小。因此，提供了电阻率为100Ωm或更大的高电阻，低氧和高强度硅晶片，并且形成具有0.2μm大小的氧沉淀物（BMD），以便具有高密度的1×10 4/4以上。

4. 发明授权

US07220308B2 Manufacturing method of high resistivity silicon single crystal 有权
标题翻译：高电阻率硅单晶的制造方法
公开(公告)号：US07220308B2
公开(公告)日：2007-05-22
申请号：US10828555
申请日：2004-04-21
申请人： Nobumitsu Takase , Hideshi Nishikawa , Makoto Ito , Koujl Sueoka , Shinsuke Sadamitsu
发明人： Nobumitsu Takase , Hideshi Nishikawa , Makoto Ito , Koujl Sueoka , Shinsuke Sadamitsu
IPC分类号： C30B15/20
CPC分类号： C30B29/06 , C30B15/00
摘要： To suppress a fluctuation in resistivity around a target value to thereby stably manufacture high resistivity silicon single crystals having almost the same resistivity values in a manufacturing method wherein a silicon raw material is molten to manufacture a high resistivity silicon single crystal in the range of from 100 to 2000 Ω cm with a CZ method. In a case where poly-silicon produced with a Siemens method using trichlorosilane as raw material is used as the silicon raw material, an impurity concentration in the silicon raw material is selected so as to be controlled in the range of from −5 to 50 ppta method in terms of (a donor concentration—an acceptor concentration) and the selected poly-silicon is used. In a case of a MCZ method, the poly-silicon is selected in the range of from −25 to 20 ppta and the selected poly-silicon is used. Instead of the raw material, poly-silicon produced with a Siemens method using monosilane as raw material is used. Alternatively, a silicon crystal manufactured with a CZ method or a MCZ method using poly-silicon raw material is used.
摘要翻译：为了抑制围绕目标值的电阻率的波动，从而在将硅原料熔融以制造范围为100的高电阻率硅单晶的制造方法中稳定地制造具有几乎相同的电阻率值的高电阻率硅单晶到2000欧米加厘米与CZ方法。在使用以三氯硅烷为原料的西门子方法制造的多晶硅作为硅原料的情况下，选择硅原料中的杂质浓度以控制在-5〜50ppta的范围内使用（供体浓度 - 受体浓度）和选择的多晶硅的方法。在MCZ方法的情况下，多晶硅的选择范围为-25〜20ppta，使用所选择的多晶硅。使用以硅烷为原料的西门子法生产的多晶硅代替原料。或者，使用以CZ法制造的硅晶体或使用多晶硅原料的MCZ法。

5. 发明授权

US07226571B2 High resistivity silicon wafer and method for fabricating the same 有权
标题翻译：高电阻率硅晶片及其制造方法
公开(公告)号：US07226571B2
公开(公告)日：2007-06-05
申请号：US10964728
申请日：2004-10-15
申请人： Nobumitsu Takase , Shinsuke Sadamitsu , Takayuki Kihara , Masataka Hourai
发明人： Nobumitsu Takase , Shinsuke Sadamitsu , Takayuki Kihara , Masataka Hourai
IPC分类号： C30B15/20
CPC分类号： H01L21/3225
摘要： A high resistivity p type silicon wafer with a resistivity of 100 Ωcm or more, in the vicinity of the surface being formed denuded zone, wherein when a heat treatment in the device fabrication process is performed, a p/n type conversion layer due to thermal donor generation is located at a depth to be brought into contact with neither any device active region nor depletion layer region formed in contact therewith or at a depth more than 8 μm from the surface, and a method for fabricating the same. The high resistivity silicon wafer can cause the influence of thermal donors to disappear without reducing the soluble oxygen concentration in the wafer, whereby even if various heat treatments are performed in the device fabrication process, devices such as CMOS that offer superior characteristics can be fabricated. The wafer has wide application as a substrate for a high-frequency integrated circuit device.
摘要翻译：在形成表面的附近，具有电阻率为100Ωm或更大的高电阻率p型硅晶片，其中当进行器件制造工艺中的热处理时，由于热供体而导致的ap / n型转换层一代位于与表面形成接触或超过8μm深度的任何器件有源区和耗尽层区域的深度上，以及其制造方法。高电阻率硅晶片可以引起供体的影响而不降低晶片中的可溶性氧浓度，由此即使在器件制造工艺中进行各种热处理，也可以制造诸如CMOS的器件，其提供优异的特性。该晶片作为高频集成电路器件的基板具有广泛的应用。

6. 发明申请

US20050250349A1 High-resistance silicon wafer and process for producing the same 有权
标题翻译：高电阻硅晶片及其制造方法
公开(公告)号：US20050250349A1
公开(公告)日：2005-11-10
申请号：US10519837
申请日：2003-06-30
申请人： Shinsuke Sadamitsu , Nobumitsu Takase , Hiroyuki Takao , Koji Sueoka , Masataka Horai
发明人： Shinsuke Sadamitsu , Nobumitsu Takase , Hiroyuki Takao , Koji Sueoka , Masataka Horai
IPC分类号： C30B29/06 , C30B33/00 , H01L21/322 , H01L21/762 , H01L21/00 , H01L21/336 , H01L29/15 , H01L31/0312
CPC分类号： C30B33/00 , C30B29/06 , H01L21/3225 , H01L21/76243 , Y10T428/21
摘要： A high-resistance silicon wafer is manufactured, in which a gettering ability and economical efficiency is excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is to be implemented on the side of a device manufacturer. In order to implement the above, a high-temperature heat treatment at 1100° C. or higher is performed on a carbon doped high-resistance and high-oxygen silicon wafer in which specific resistivity is 100 Ωcm or more and a carbon concentration is 5×1015 to 5×1017 atoms/cm3 so that a remaining oxygen concentration becomes 6.5×1017 atoms/cm3 or more (Old-ASTM). As this high-temperature treatment, an OD treatment for forming a DZ layer on a wafer surface, a high-temperature annealing treatment for eliminating a COP on the surface layer, a high-temperature heat treatment for forming a BOX layer in a SIMOX wafer manufacturing process and the like can be used.
摘要翻译：制造高电阻硅晶片，其中吸收能力和经济效率优异，并且在用于形成电路的热处理中有效地防止氧热供体被产生，该电路将在器件的一侧制造商。为了实现上述，在比电阻率为100Ω·以上且碳浓度为5×10 6的碳掺杂高电阻和高氧硅晶片上进行1100℃以上的高温热处理 15至15×10 17原子/ cm 3，使得剩余的氧浓度为6.5×10 17原子/ cm 3， SUP> 3以上（旧ASTM）。作为这种高温处理，在晶片表面上形成DZ层的OD处理，用于消除表面层上的COP的高温退火处理，在SIMOX晶片中形成BOX层的高温热处理可以使用制造工艺等。

7. 发明申请

US20050127477A1 High resistivity silicon wafer and method for fabricating the same 有权
标题翻译：高电阻率硅晶片及其制造方法
公开(公告)号：US20050127477A1
公开(公告)日：2005-06-16
申请号：US10964728
申请日：2004-10-15
申请人： Nobumitsu Takase , Shinsuke Sadamitsu , Takayuki Kihara , Masataka Hourai
发明人： Nobumitsu Takase , Shinsuke Sadamitsu , Takayuki Kihara , Masataka Hourai
IPC分类号： H01L21/322 , H01L21/324 , H01L29/00
CPC分类号： H01L21/3225
摘要： A high resistivity p type silicon wafer with a resistivity of 100 Ωcm or more, in the vicinity of the surface being formed denuded zone, wherein when a heat treatment in the device fabrication process is performed, a p/n type conversion layer due to thermal donor generation is located at a depth to be brought into contact with neither any device active region nor depletion layer region formed in contact therewith or at a depth more than 8 μm from the surface, and a method for fabricating the same. The high resistivity silicon wafer can cause the influence of thermal donors to disappear without reducing the soluble oxygen concentration in the wafer, whereby even if various heat treatments are performed in the device fabrication process, devices such as CMOS that offer superior characteristics can be fabricated. The wafer has wide application as a substrate for a high-frequency integrated circuit device.
摘要翻译：在形成表面的附近，具有电阻率为100Ωm或更大的高电阻率p型硅晶片，其中当进行器件制造工艺中的热处理时，由于热供体而导致的ap / n型转换层一代位于与表面形成接触或超过8μm深度的任何器件有源区和耗尽层区域的深度上，以及其制造方法。高电阻率硅晶片可以引起供体的影响而不降低晶片中的可溶性氧浓度，由此即使在器件制造工艺中进行各种热处理，也可以制造诸如CMOS的器件，其提供优异的特性。该晶片作为高频集成电路器件的基板具有广泛的应用。

8. 发明授权

US07316745B2 High-resistance silicon wafer and process for producing the same 有权
标题翻译：高电阻硅晶片及其制造方法
公开(公告)号：US07316745B2
公开(公告)日：2008-01-08
申请号：US10519837
申请日：2003-06-30
申请人： Shinsuke Sadamitsu , Nobumitsu Takase , Hiroyuki Takao , Koji Sueoka , Masataka Horai
发明人： Shinsuke Sadamitsu , Nobumitsu Takase , Hiroyuki Takao , Koji Sueoka , Masataka Horai
IPC分类号： C30B29/06 , H01L21/322 , H01L21/324
CPC分类号： C30B33/00 , C30B29/06 , H01L21/3225 , H01L21/76243 , Y10T428/21
摘要： A high-resistance silicon wafer is manufactured, in which a gettering ability and economical efficiency is excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is to be implemented on the side of a device manufacturer. In order to implement the above, a high-temperature heat treatment at 1100° C. or higher is performed on a carbon doped high-resistance and high-oxygen silicon wafer in which specific resistivity is 100 Ωcm or more and a carbon concentration is 5×1015 to 5×1017 atoms/cm3 so that a remaining oxygen concentration becomes 6.5×1017 atoms/cm3 or more (Old-ASTM). As this high-temperature treatment, an OD treatment for forming a DZ layer on a wafer surface, a high-temperature annealing treatment for eliminating a COP on the surface layer, a high-temperature heat treatment for forming a BOX layer in a SIMOX wafer manufacturing process and the like can be used.
摘要翻译：制造高电阻硅晶片，其中吸收能力和经济效率优异，并且在用于形成电路的热处理中有效地防止氧热供体被产生，该电路将在器件的一侧制造商。为了实现上述，在比电阻率为100Ω·以上且碳浓度为5×10 6的碳掺杂高电阻和高氧硅晶片上进行1100℃以上的高温热处理 15至15×10 17原子/ cm 3，使得剩余的氧浓度为6.5×10 17原子/ cm 3， SUP> 3以上（旧ASTM）。作为这种高温处理，在晶片表面上形成DZ层的OD处理，用于消除表面层上的COP的高温退火处理，在SIMOX晶片中形成BOX层的高温热处理可以使用制造工艺等。

9. 发明授权

US06641888B2 Silicon single crystal, silicon wafer, and epitaxial wafer. 有权
标题翻译：硅单晶，硅晶片和外延晶片。
公开(公告)号：US06641888B2
公开(公告)日：2003-11-04
申请号：US10055340
申请日：2002-01-25
申请人： Eiichi Asayama , Masataka Horai , Shigeru Umeno , Shinsuke Sadamitsu , Yasuo Koike , Kouji Sueoka , Hisashi Katahama
发明人： Eiichi Asayama , Masataka Horai , Shigeru Umeno , Shinsuke Sadamitsu , Yasuo Koike , Kouji Sueoka , Hisashi Katahama
IPC分类号： C30B2906
CPC分类号： C30B15/00 , C30B29/06 , Y10T428/21
摘要： There are provided silicon single crystal, silicon wafer, and epitaxial wafer having a sufficient gettering effect suitable for a large-scale integrated device. The silicon single crystal which is suitable for an epitaxial wafer is grown with nitrogen doping at a concentration of 1×1013 atoms/cm3 or more, or with nitrogen doping at a concentration of 1×1012 atoms/cm3 and carbon doping at a concentration of 0.1×1016−5×1016 atoms/cm3 and/or boron doping at a concentration of 1×1017 atoms/cm3 or more. The silicon wafer is produced by slicing from the silicon single crystal, and an epitaxial layer is grown on a surface of the silicon wafer to produce the epitaxial wafer. The present invention provides an epitaxial wafer for a large-scale integrated device having no defects in a device-active region and having an excellent gettering effect without performance of an extrinsic or intrinsic gettering treatment.
摘要翻译：提供了具有适合于大规模集成器件的足够的吸气效应的硅单晶，硅晶片和外延晶片。适用于外延晶片的硅单晶以1×10 13原子/ cm 3或更高的浓度氮掺杂或以1×10 12原子/ cm 3的浓度氮掺杂生长并且以0.1×10 16〜10×10 16原子/ cm 3的浓度进行碳掺杂和/或以1×10 17个/ cm 3以上的浓度掺杂的硼。通过从硅单晶切片制造硅晶片，并且在硅晶片的表面上生长外延层以制造外延晶片。本发明提供了一种用于大规模集成器件的外延晶片，其在器件活性区域中没有缺陷，并且具有优异的吸气效应，而没有外部或内在的吸气处理。

10. 发明申请

US20090017291A1 Silicon epitaxial wafer and production method for same 审中-公开
标题翻译：硅外延片及其制作方法相同
公开(公告)号：US20090017291A1
公开(公告)日：2009-01-15
申请号：US11661724
申请日：2005-08-30
申请人： Shinsuke Sadamitsu , Masataka Hourai
发明人： Shinsuke Sadamitsu , Masataka Hourai
IPC分类号： B32B5/00 , H01L21/205
CPC分类号： C30B29/06 , C30B15/00 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/3225 , H01L27/146 , H01L31/186 , Y02P70/521 , Y10T428/265
摘要： A silicon epitaxial wafer of the invention comprises a silicon single crystal wafer sliced from a CZ silicon ingot doped with carbon in a concentration range of not less than 5×1015 atoms/cm3 and not more than 5×1017 atoms/cm3 and an epitaxial layer consisting of a silicon single crystal epitaxially grown on a front surface of the silicon single crystal wafer. A polycrystalline silicon layer having a thickness of not less than 0.5 μm and not more than 1.5 μm is formed on a back surface of the silicon single crystal wafer.
摘要翻译：本发明的硅外延晶片包括从掺杂有不少于5×10 15原子/ cm 3且不大于5×10 17原子/ cm 3的浓度的碳的CZ硅锭切片的硅单晶晶片和由硅构成的外延层在硅单晶晶片的正面上外延生长的单晶。在硅单晶晶片的背面形成厚度不小于0.5μm且不大于1.5μm的多晶硅层。

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