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1. 发明申请

US20060141750A1 Semiconductor integrated device and method for manufacturing same 审中-公开
标题翻译：半导体集成器件及其制造方法
公开(公告)号：US20060141750A1
公开(公告)日：2006-06-29
申请号：US10529465
申请日：2003-11-12
申请人： Nobuhiro Suzuki , Kenji Imai , Isaya Kitamura , Keiichi Yamaguchi
发明人： Nobuhiro Suzuki , Kenji Imai , Isaya Kitamura , Keiichi Yamaguchi
IPC分类号： H01L21/78
CPC分类号： H01L24/10 , H01L21/3043 , H01L21/76898 , H01L21/78 , H01L23/3114 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05548 , H01L2224/05569 , H01L2224/13 , H01L2224/13099 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/14 , H01L2924/00 , H01L2224/05599
摘要： A method for manufacturing a semiconductor integrated device includes steps of forming an integrated circuit element on a semiconductor substrate, forming internal wiring, forming a groove along a scribe line on a back surface of the semiconductor substrate to expose a portion of the internal wiring, forming a metal film covering at least the groove, patterning the metal film to form external wiring and removing the metal film at a bottom portion of the groove, forming a protection film covering the external wiring and the bottom portion of the groove, and separating the semiconductor substrate along the scribe line.
摘要翻译：一种半导体集成器件的制造方法，其特征在于，包括在半导体衬底上形成集成电路元件，形成内部配线的步骤，在半导体衬底的背面沿着划线形成沟槽，露出内部配线的一部分，形成至少覆盖所述槽的金属膜，图案化所述金属膜以形成外部布线，并且在所述槽的底部除去所述金属膜，形成覆盖所述外部布线和所述槽的底部的保护膜，以及将所述半导体基板沿着划线。

2. 发明授权

US08204454B2 Distortion compensator apparatus, amplifier apparatus, transmitter, and method of compensating distortion 有权
标题翻译：失真补偿装置，放大器装置，发射机和补偿失真的方法
公开(公告)号：US08204454B2
公开(公告)日：2012-06-19
申请号：US12303381
申请日：2007-05-29
申请人： Atsushi Yamaoka , Keiichi Yamaguchi
发明人： Atsushi Yamaoka , Keiichi Yamaguchi
IPC分类号： H04B1/04
CPC分类号： H03F1/3288 , H03F1/3294 , H03F2200/336 , H03F2201/3233
摘要： This distortion compensator apparatus is a distortion compensator apparatus compensating nonlinearity of an amplifier and includes: a memory storing a compensation parameter used for correcting an input signal of the amplifier; a compensator correcting the input signal of the amplifier based on the compensation parameter; and an update controller updating the compensation parameter according to an operation state of the amplifier.
摘要翻译：该失真补偿装置是补偿放大器的非线性的失真补偿装置，包括：存储用于校正放大器的输入信号的补偿参数的存储器; 补偿器，基于所述补偿参数校正所述放大器的输入信号; 以及更新控制器，根据放大器的运行状态更新补偿参数。

3. 发明授权

US07557017B2 Method of manufacturing semiconductor device with two-step etching of layer 有权
标题翻译：制造半导体器件的方法，具有两步蚀刻层
公开(公告)号：US07557017B2
公开(公告)日：2009-07-07
申请号：US11191276
申请日：2005-07-28
申请人： Hiroshi Yamada , Keiichi Yamaguchi
发明人： Hiroshi Yamada , Keiichi Yamaguchi
IPC分类号： H01L21/00
CPC分类号： H01L24/10 , H01L21/78 , H01L23/3114 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05023 , H01L2224/05124 , H01L2224/05147 , H01L2224/05548 , H01L2224/05569 , H01L2224/05624 , H01L2224/05647 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/00 , H01L2924/00014
摘要： The invention is directed to improvement of reliability of a process of separating a layer to be patterned such as a wiring layer in a semiconductor device manufacturing method. A wiring layer is formed on a back surface of a semiconductor substrate. A third resist layer (positive resist layer) is formed on the wiring layer, having an opening in a predetermined region along a dicing line at a bottom of the opening, and the wiring layer is etched using the third resist layer as a mask. After the third resist layer is removed, a fourth resist layer (negative resist layer) is formed on the wiring layer so as to leave the wiring layer in a region of a predetermined pattern, and the wiring layer is etched using the fourth resist layer as a mask. The wiring layer is thus patterned so as to form the predetermined pattern and be separated at the predetermined region along the dicing line at the bottom of the opening without fail.
摘要翻译：本发明旨在提高半导体器件制造方法中分离诸如布线层的待图案化层的工艺的可靠性。在半导体基板的背面形成配线层。在布线层上形成第三抗蚀剂层（正性抗蚀剂层），沿着开口底部的切割线在预定区域具有开口，并且使用第三抗蚀剂层作为掩模蚀刻布线层。在除去第三抗蚀剂层之后，在布线层上形成第四抗蚀剂层（负抗蚀剂层），以便将布线层留在预定图案的区域中，并且使用第四抗蚀剂层将布线层蚀刻一个面具因此，布线层被图案化以形成预定图案，并且在开口底部的切割线的预定区域处被分离。

4. 发明申请

US20060240176A1 Method for manufacturing confectionery, freeze drying method and freeze-dried confectionery 审中-公开
标题翻译：制作糖果，冷冻干燥方法和冷冻干燥糖果的方法
公开(公告)号：US20060240176A1
公开(公告)日：2006-10-26
申请号：US11391514
申请日：2006-03-28
申请人： Keiichi Yamaguchi , Hironobu Tsujiguchi , Hiroyuki Kamijo , Shunzo Oike
发明人： Keiichi Yamaguchi , Hironobu Tsujiguchi , Hiroyuki Kamijo , Shunzo Oike
IPC分类号： A23G3/00
CPC分类号： A23G1/0046 , A23G1/305 , A23G7/0093 , A23G9/52 , A23G2200/12 , A23G2200/14 , A23G2220/20 , A23L3/44
摘要： A method for freeze drying confectionary is provided, whereby a confectionary is provided that can be stored for long periods of time without deformation. Further, a confectionery is provided using cream comprising 28 to 33 parts by weight of cream having a milk fat content of 42% to 48%, 28 to 33 parts by weight of cream having a milk fat content of 32% to 38%, 28 to 33 parts by weight of vegetable-based cream, and 5 to 10 parts by weight of sugar. The confectionery is freeze dried by: freezing the confectionery; subsequently setting the drying pressure to 0.60 to 0.65 Torr; performing primary sublimation by drying at a temperature of 25° C. to 40° C., for 3 to 4 hours; subsequently performing secondary sublimation by drying at a temperature of 60° C. to 70° C. for 18 to 20 hours; and further performing tertiary sublimation by drying at a temperature of 35° C. to 45° C. for 1.5 to 4.5 hours.
摘要翻译：提供一种冷冻干燥糖果的方法，由此提供可以长时间储存而不变形的糖果。此外，使用含有28〜33重量份乳脂肪含量为42〜48重量％的奶油，28〜33重量份乳脂含量为32〜38重量％的奶油，28 至33重量份的植物性霜剂和5至10重量份的糖。糖果通过以下方式冻结：冻结糖果; 随后将干燥压力设定为0.60〜0.65乇; 通过在25℃至40℃的温度下干燥3至4小时进行初级升华; 随后通过在60℃至70℃的温度下干燥18至20小时进行二次升华; 并进一步通过在35℃至45℃的温度下干燥1.5至4.5小时进行三次升华。

5. 发明授权

US06927625B2 High frequency circuit using high output amplifier cell block and low output amplifier cell block 失效
公开(公告)号：US06927625B2
公开(公告)日：2005-08-09
申请号：US10927165
申请日：2004-08-27
申请人： Keiichi Yamaguchi
发明人： Keiichi Yamaguchi
IPC分类号： H03F3/68 , H01P5/107 , H03F1/02 , H03F3/213 , H03F3/24 , H03F3/72 , H04B1/04
CPC分类号： H03F1/0283 , H01L24/48 , H01L24/49 , H01L2223/6644 , H01L2224/48091 , H01L2224/49111 , H01L2224/49175 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01027 , H01L2924/0105 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H03F3/72 , H03F2203/7236 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A high frequency circuit capable of realizing a power amplifier with a wide dynamic range in which it is hard to degrade the power addition efficiency at low output is formed by using a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signals, and a low output amplifier cell block configured to amplify input signals at a time of low output power, in which a DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to input/output signals.

6. 发明授权

US06876270B2 Symmetric microwave filter and microwave integrated circuit merging the same 失效
标题翻译：对称微波滤波器和微波集成电路合并相同
公开(公告)号：US06876270B2
公开(公告)日：2005-04-05
申请号：US10397258
申请日：2003-03-27
申请人： Naoko Ono , Keiichi Yamaguchi
发明人： Naoko Ono , Keiichi Yamaguchi
IPC分类号： H01L27/04 , H01L21/822 , H01P1/201 , H03F3/60 , H03H7/06 , H01P5/00
CPC分类号： H01P1/2013
摘要： A microwave filter is disposed on a substrate. The microwave filter is configured to connect a first microwave transmission line to a second microwave transmission line, configured such that a signal propagates from the first microwave transmission line to the second microwave transmission line. The microwave filter encompasses a highpass component of filter disposed in a symmetrical configuration with respect to a median plane placed perpendicular to the surface of the substrate, including the central axis of the first and second microwave transmission lines; and a lowpass component of filter connected parallel with the highpass component of filter, the lowpass component of filter being disposed in a symmetrical configuration with respect to the median plane.
摘要翻译：微波滤波器设置在基板上。微波滤波器被配置为将第一微波传输线连接到第二微波传输线，其被配置为使得信号从第一微波传输线传播到第二微波传输线。微波滤波器包括相对于垂直于衬底表面放置的中间平面的对称构型布置的滤波器的高通分量，包括第一和第二微波传输线的中心轴线; 以及与滤波器的高通分量并联连接的滤波器的低通分量，滤波器的低通分量相对于中间平面布置成对称的结构。

7. 发明授权

US07974654B2 Communication apparatus performing key feature extraction for cognitive radio system 有权
标题翻译：对认知无线电系统执行关键特征提取的通信装置
公开(公告)号：US07974654B2
公开(公告)日：2011-07-05
申请号：US11888559
申请日：2007-08-01
申请人： Tazuko Tomioka , Keiichi Yamaguchi , Tomoya Horiguchi
发明人： Tazuko Tomioka , Keiichi Yamaguchi , Tomoya Horiguchi
IPC分类号： H04M1/00
CPC分类号： H04W16/14 , H04W28/06
摘要： A communication apparatus, includes unit extracting a reception key feature of a temporal change in received power in each frequency band contained in a received signal, unit storing, in correspondence with one another, a system name of a system which uses the frequency band, event information indicating that a communication apparatus belonging to the system starts or stops transmission, and a transmission key feature of a temporal waveform change shape of a transmission signal from a communication apparatus belonging to the system, a transmission key feature corresponding to the event information, unit determining whether there is any transmission key feature matching the reception key feature, by comparing the reception key feature with the transmission key feature, and unit selecting, when the determination unit determines that there is a matched transmission key feature, the event information and the system name which correspond to the transmission key feature from the storage unit.
摘要翻译：一种通信装置，包括提取包含在接收信号中的每个频带中的接收功率的时间变化的接收关键特征的单元，该单元相对应地存储使用该频带的系统的系统名称，事件指示属于系统的通信设备的信息开始或停止发送的信息，以及来自属于系统的通信设备的发送信号的时间波形变化形状的传输密钥特征，与事件信息对应的传输密钥特征，单元通过将接收密钥特征与传输密钥特征进行比较来确定是否存在与接收密钥特征相匹配的传输密钥特征，以及当确定单元确定存在匹配的传输密钥特征时，单元选择事件信息和系统与存储单元的传输键特征对应的名称。

8. 发明申请

US20100159856A1 Distortion compensator, distortion compensation method, and transmitter 有权
标题翻译：失真补偿器，失真补偿方法和变送器
公开(公告)号：US20100159856A1
公开(公告)日：2010-06-24
申请号：US12585443
申请日：2009-09-15
申请人： Takayuki Kato , Atsushi Yamaoka , Keiichi Yamaguchi
发明人： Takayuki Kato , Atsushi Yamaoka , Keiichi Yamaguchi
IPC分类号： H04B1/04 , H03F1/26
CPC分类号： H03F1/3258 , H03F1/3247 , H03F3/19 , H03F3/245 , H03F2200/204 , H03F2200/336 , H03F2200/78 , H04B1/0475
摘要： A distortion compensator for reducing a level of a distortion component included in an output analog signal of an amplifier, includes: an A/D converter to convert the output analog signal of the amplifier into a digital output signal; a comparator to generate a distortion characteristic of the amplifier based on a digital input signal and the digital output signal; a rate controller to control a sampling rate of the A/D converter based on the digital input signal and the digital output signal; a predistorter to multiply the digital input signal and a compensation value for compensating the amplifier, the compensation value being calculated based on the digital input signal and the distortion characteristic of the amplifier; and a D/A converter to convert multiplication result of the predistorter into an analog input signal to input the analog input signal to the amplifier.
摘要翻译：一种用于降低包括在放大器的输出模拟信号中的失真分量电平的失真补偿器，包括：A / D转换器，用于将放大器的输出模拟信号转换为数字输出信号; 比较器，用于基于数字输入信号和数字输出信号产生放大器的失真特性; 速率控制器，其基于所述数字输入信号和所述数字输出信号来控制所述A / D转换器的采样率; 用于对数字输入信号进行倍增的预失真器和用于补偿放大器的补偿值，基于数字输入信号和放大器的失真特性计算补偿值; 以及D / A转换器，用于将预失真器的相乘结果转换为模拟输入信号，以将模拟输入信号输入到放大器。

9. 发明授权

US07489910B2 Wireless transmitter and amplifier 有权
标题翻译：无线发射机和放大器
公开(公告)号：US07489910B2
公开(公告)日：2009-02-10
申请号：US11387568
申请日：2006-03-23
申请人： Takayuki Kato , Hiroshi Yoshida , Ichiro Seto , Keiichi Yamaguchi
发明人： Takayuki Kato , Hiroshi Yoshida , Ichiro Seto , Keiichi Yamaguchi
IPC分类号： H03C7/02 , H04B1/02
CPC分类号： H03F3/72 , H03F1/0288 , H03F3/24 , H03F3/602 , H03F2200/111 , H03F2200/423 , H03F2200/429 , H04B1/0483 , H04B2001/0408
摘要： There is provided with an amplifier comprising: first and second power amplifiers; a first path configured to output first and second input signals to the first and second power amplifiers; a second path configured to divide a first input signal, output one of divided signals to the first power amplifier and output the other divided signal to the second power amplifier; a first path changeover unit configured to change over the first and second paths; a third path configured to output first and second power amplified signals from the first and second power amplifiers; a fourth path configured to combines a first power amplified signal through an impedance conversion unit from the first power amplifier and a second power amplified signal from the second power amplifier at a combining point and output a combined signal; and a second path changeover unit configured to changeover the third and fourth paths.
摘要翻译：提供了一种放大器，包括：第一和第二功率放大器; 第一路径，被配置为将第一和第二输入信号输出到所述第一和第二功率放大器; 第二路径，被配置为分割第一输入信号，将分频信号中的一个输出到第一功率放大器，并将另一个分频信号输出到第二功率放大器; 第一路径切换单元，被配置为切换第一和第二路径; 第三路径，被配置为从所述第一和第二功率放大器输出第一和第二功率放大信号; 第四路径，被配置为通过来自第一功率放大器的阻抗转换单元和来自第二功率放大器的组合点的第二功率放大信号组合第一功率放大信号并输出组合信号; 以及第二路径切换单元，被配置为切换第三路径和第四路径。

10. 发明申请

US20080093708A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080093708A1
公开(公告)日：2008-04-24
申请号：US11956160
申请日：2007-12-13
申请人： Takashi Noma , Katsuhiko Kitagawa , Hisao Otsuka , Akira Suzuki , Yoshinori Seki , Yukihiro Takao , Keiichi Yamaguchi , Motoaki Wakui , Masanori Iida
发明人： Takashi Noma , Katsuhiko Kitagawa , Hisao Otsuka , Akira Suzuki , Yoshinori Seki , Yukihiro Takao , Keiichi Yamaguchi , Motoaki Wakui , Masanori Iida
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L2221/68327 , H01L2221/68372 , H01L2224/02313 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2224/131 , H01L2224/13144 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00014 , H01L2224/13099
摘要： A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.
摘要翻译：改进了以芯片尺寸封装形成的半导体器件的制造方法，以提高产量和可靠性。仅在存在第一布线的半导体基板的区域中形成露出第一布线的窗口。结果，增加了通过绝缘膜和树脂粘合到支撑体的半导体衬底的面积，以防止支撑体中的裂纹和半导体衬底与支撑体的分离。在形成窗口之后沿着切割线形成狭缝，用保护膜覆盖狭缝，然后将半导体基板切割成单独的半导体管芯。因此，可以防止在切割时由刀片接触而导致的半导体管芯的切割面或边缘处的分离。

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