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1. 发明申请

US20140281778A1 BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL 有权
标题翻译：内置自检（BIST）与时钟控制
公开(公告)号：US20140281778A1
公开(公告)日：2014-09-18
申请号：US13967337
申请日：2013-08-14
申请人： Nisar Ahmed , Anurag Jindal , Nipun Mahajan
发明人： Nisar Ahmed , Anurag Jindal , Nipun Mahajan
IPC分类号： G01R31/3177
CPC分类号： G06F11/27 , G01R31/31727 , G01R31/3177 , G01R31/318552 , G01R31/3187
摘要： A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode.
摘要翻译：一种处理系统包括：时钟发生器电路，被配置为接收主时钟信号并输出多个时钟信号，其中所述多个时钟信号在内置自检（BIST）模式期间具有第一频率，并且多个时钟信号移位捕获时钟发生器电路。每个移位捕获时钟发生器电路包括时钟门电路和时钟分频器电路，并且被配置为接收多个时钟信号中相应的一个时钟信号。至少一个时钟分频器电路在BIST模式期间将多个时钟信号之一的第一频率改变为第二频率。

2. 发明授权

US09298572B2 Built-in self test (BIST) with clock control 有权
标题翻译：内置自检（BIST），具有时钟控制功能
公开(公告)号：US09298572B2
公开(公告)日：2016-03-29
申请号：US13967337
申请日：2013-08-14
申请人： Nisar Ahmed , Anurag Jindal , Nipun Mahajan
发明人： Nisar Ahmed , Anurag Jindal , Nipun Mahajan
IPC分类号： G01R31/28 , G06F11/27 , G01R31/3177 , G01R31/3185 , G01R31/3187 , G01R31/317
CPC分类号： G06F11/27 , G01R31/31727 , G01R31/3177 , G01R31/318552 , G01R31/3187
摘要： A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode.
摘要翻译：一种处理系统包括：时钟发生器电路，被配置为接收主时钟信号并输出多个时钟信号，其中所述多个时钟信号在内置自检（BIST）模式期间具有第一频率，并且多个时钟信号移位捕获时钟发生器电路。每个移位捕获时钟发生器电路包括时钟门电路和时钟分频器电路，并且被配置为接收多个时钟信号中相应的一个时钟信号。至少一个时钟分频器电路在BIST模式期间将多个时钟信号之一的第一频率改变为第二频率。

3. 发明申请

US20160109514A1 STRUCTURAL TESTING OF INTEGRATED CIRCUITS 有权
标题翻译：集成电路的结构测试
公开(公告)号：US20160109514A1
公开(公告)日：2016-04-21
申请号：US14514402
申请日：2014-10-15
申请人： Anurag Jindal , Nipun Mahajan
发明人： Anurag Jindal , Nipun Mahajan
IPC分类号： G01R31/3177
CPC分类号： G01R31/318572 , G01R31/3172 , G01R31/31908
摘要： An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature.
摘要翻译：在扫描测试和功能模式中可操作的集成电路（IC）包括扫描焊盘，扫描焊盘，扫描链，压缩器，解压缩器，测试控制寄存器和扫描控制器。扫描控制器包括多输入移位寄存器（MISR），反相器和多个逻辑门。扫描和扫描焊盘分别接收扫描测试数据和屏蔽信号。解压缩器向扫描链提供解压缩的扫描测试数据，其基于解压缩的扫描测试数据生成功能响应。压缩机为扫描控制器提供压缩的功能响应。逻辑门分别从压缩器和对应的扫描输出焊盘接收压缩的功能响应和掩蔽信号，并产生相应的屏蔽信号。掩蔽信号掩蔽解压缩的功能响应中的非确定性值。 MISR接收被屏蔽的信号并产生无差错的签名。

4. 发明授权

US09599673B2 Structural testing of integrated circuits 有权
公开(公告)号：US09599673B2
公开(公告)日：2017-03-21
申请号：US14514402
申请日：2014-10-15
申请人： Anurag Jindal , Nipun Mahajan
发明人： Anurag Jindal , Nipun Mahajan
IPC分类号： G01R31/3177 , G01R31/3185 , G01R31/40 , G01R31/319 , G01R31/317
CPC分类号： G01R31/318572 , G01R31/3172 , G01R31/31908
摘要： An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature.

5. 发明授权

US09201116B1 Method of generating test patterns for detecting small delay defects 有权
标题翻译：生成用于检测小延迟缺陷的测试模式的方法
公开(公告)号：US09201116B1
公开(公告)日：2015-12-01
申请号：US14340572
申请日：2014-07-25
申请人： Anurag Jindal , Naman Gupta , Sagar Kataria , Pragya Shukla
发明人： Anurag Jindal , Naman Gupta , Sagar Kataria , Pragya Shukla
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： G01R31/318328
摘要： A method of generating test patterns for testing a semiconductor processor for small delay defects (SDD) includes modifying interconnect delay values of interconnect paths by introducing values corresponding to (i) set-up and clock to Q delays of elements in the paths and (ii) latencies of associated clock networks. Critical nodes are selected and test patterns targeting the selected critical nodes are generated using timing slack resulting from the modified interconnect delays. A first selection of nodes that are critical in at-speed scan mode testing and a second selection of nodes that are critical in functional mode testing are made by static timing analysis (STA). Only the nodes featuring in both the first and second selections are selected for targeting small delay defects using at-speed scan test patterns.
摘要翻译：产生用于测试用于小延迟缺陷（SDD）的半导体处理器的测试图案的方法包括通过将对应于（i）设置和时钟的值引入到路径中的元素的Q延迟来修改互连路径的互连延迟值，）相关时钟网络的延迟。选择关键节点，并使用由修改的互连延迟导致的定时松弛来生成针对所选关键节点的测试模式。在速度扫描模式测试中关键的节点的第一选择和在功能模式测试中关键的节点的第二选择是通过静态时序分析（STA）进行的。选择在第一和第二选择中特征的节点，以使用高速扫描测试图案来瞄准小的延迟缺陷。

6. 发明授权

US08956974B2 Devices, systems, and methods related to planarizing semiconductor devices after forming openings 有权
标题翻译：与形成开口后的半导体器件平面化有关的装置，系统和方法
公开(公告)号：US08956974B2
公开(公告)日：2015-02-17
申请号：US13538272
申请日：2012-06-29
申请人： Wayne H. Huang , Anurag Jindal
发明人： Wayne H. Huang , Anurag Jindal
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/02164 , H01L21/0217 , H01L21/304 , H01L21/31053 , H01L21/3212 , H01L21/743 , H01L21/76831 , H01L21/7684 , H01L21/76883
摘要： Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings. The method further includes forming a metal layer including metal plugs within the openings and excess metal. The excess metal and the excess dielectric material are simultaneously chemically-mechanically removed using a slurry including ceria and ammonium persulfate. The slurry is selected to cause selectivity for removing the excess dielectric material relative to the stop layer greater than about 5:1 as well as selectivity for removing the excess dielectric material relative to the excess metal from about 0.5:1 to about 1.5:1.
摘要翻译：本文公开了制造半导体器件的方法。根据特定实施例配置的方法包括形成包含电介质材料的阻挡层和电介质衬垫，所述阻挡层和电介质衬垫沿着半导体器件的开口的侧壁（例如贯穿衬底开口）和开口外的多余电介质材料。该方法还包括在开口内形成包括金属塞的金属层和多余的金属。使用包括二氧化铈和过硫酸铵的浆料同时化学机械地除去多余的金属和过量的电介质材料。选择浆料以引起相对于止挡层去除多余电介质材料的选择性大于约5:1，以及相对于多余金属从约0.5:1至约1.5:1去除多余电介质材料的选择性。

7. 发明授权

US08911558B2 Post-tungsten CMP cleaning solution and method of using the same 有权
标题翻译：钨后CMP清洗液及其使用方法
公开(公告)号：US08911558B2
公开(公告)日：2014-12-16
申请号：US13069408
申请日：2011-03-23
申请人： Hongqi Li , Anurag Jindal , Jin Lu
发明人： Hongqi Li , Anurag Jindal , Jin Lu
IPC分类号： B08B3/12 , B08B6/00 , B08B7/00 , B08B7/02 , C25C1/00 , C25F3/30 , C25F5/00 , C11D11/00 , C11D7/26 , H01L21/02
CPC分类号： C11D11/0047 , C11D7/265 , H01L21/02074
摘要： A post-W CMP cleaning solution consists of carboxylic acid and deionized water. The carboxylic acid may be selected from the group consisting of (1) monocarboxylic acids; (2) dicarboxylic acids; (3) tricarboxylic acids; (4) polycarboxylic acids; (5) hydroxycarboxylic acids; (6) salts of the above-described carboxylic acids; and (7) any combination thereof. The post-W CMP cleaning solution can work well without adding any other chemical additives such as surfactants, corrosion inhibitors, pH adjusting agents or chelating agents.
摘要翻译： CMP后清洁溶液由羧酸和去离子水组成。羧酸可以选自（1）一元羧酸; （2）二羧酸; （3）三羧酸; （4）多元羧酸; （5）羟基羧酸; （6）上述羧酸的盐; 和（7）其任何组合。后CMP扫描溶液可以很好的工作，而不需要添加任何其他化学添加剂，如表面活性剂，腐蚀抑制剂，pH调节剂或螯合剂。

8. 发明申请

US20140183740A1 METHODS OF EXPOSING CONDUCTIVE VIAS OF SEMICONDUCTOR DEVICES AND ASSOCIATED STRUCTURES 有权
标题翻译：半导体器件和相关结构的导电透视方法
公开(公告)号：US20140183740A1
公开(公告)日：2014-07-03
申请号：US13733508
申请日：2013-01-03
申请人： Hongqi Li , Anurag Jindal , Irina Vasilyeva
发明人： Hongqi Li , Anurag Jindal , Irina Vasilyeva
IPC分类号： H01L21/768 , H01L23/538
CPC分类号： H01L21/76865 , H01L21/7684 , H01L21/76841 , H01L21/76898 , H01L23/481 , H01L23/5384 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside surface of a substrate. A self-planarizing isolation material may be formed over the barrier material. An exposed surface of the self-planarizing isolation material may be substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of protruding material of the conductive vias may be removed to expose the conductive vias. Removal of the self-planarizing isolation material, the barrier material, and the conductive vias may be stopped after exposing at least one laterally extending portion of the barrier material.
摘要翻译：暴露半导体器件的导电通孔的方法可以包括在从衬底的背面延伸的导电通孔上保形地形成阻挡材料。可以在阻挡材料之上形成自平坦化隔离材料。自平坦化隔离材料的暴露表面可以是基本上平面的。可以去除自平坦化隔离材料的一部分，阻挡材料的一部分和导电通孔的突出材料的一部分，以露出导电通孔。在暴露阻挡材料的至少一个横向延伸部分之后，可以停止去除自平坦化隔离材料，阻挡材料和导电通孔。

9. 发明授权

US09213063B2 Reset generation circuit for scan mode exit 有权
标题翻译：复位发生电路用于扫描模式退出
公开(公告)号：US09213063B2
公开(公告)日：2015-12-15
申请号：US14225446
申请日：2014-03-26
申请人： Anurag Jindal
发明人： Anurag Jindal
IPC分类号： G01R31/3185
CPC分类号： G01R31/318583 , G01R31/318555
摘要： A reset generation circuit of an integrated circuit uses a scan data input pin as a scan mode exit control, which is enabled only when the IC reset pin of the device is active. The reset generation circuit allows a TAP controller to be scan testable yet at the same time the circuit provides a method to exit scan mode without requiring a power-up sequence or an extra pin.
摘要翻译：集成电路的复位产生电路使用扫描数据输入引脚作为扫描模式退出控制，仅在器件的IC复位引脚有效时使能。复位生成电路允许TAP控制器进行扫描测试，同时电路提供了一种退出扫描模式的方法，而不需要上电序列或额外的引脚。

10. 发明授权

US09034752B2 Methods of exposing conductive vias of semiconductor devices and associated structures 有权
标题翻译：暴露半导体器件和相关结构的导电通孔的方法
公开(公告)号：US09034752B2
公开(公告)日：2015-05-19
申请号：US13733508
申请日：2013-01-03
申请人： Hongqi Li , Anurag Jindal , Irina Vasilyeva
发明人： Hongqi Li , Anurag Jindal , Irina Vasilyeva
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/538
CPC分类号： H01L21/76865 , H01L21/7684 , H01L21/76841 , H01L21/76898 , H01L23/481 , H01L23/5384 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： Methods of exposing conductive vias of semiconductor devices may comprise conformally forming a barrier material over conductive vias extending from a backside surface of a substrate. A self-planarizing isolation material may be formed over the barrier material. An exposed surface of the self-planarizing isolation material may be substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of protruding material of the conductive vias may be removed to expose the conductive vias. Removal of the self-planarizing isolation material, the barrier material, and the conductive vias may be stopped after exposing at least one laterally extending portion of the barrier material.
摘要翻译：暴露半导体器件的导电通孔的方法可以包括在从衬底的背面延伸的导电通孔上保形地形成阻挡材料。可以在阻挡材料之上形成自平坦化隔离材料。自平坦化隔离材料的暴露表面可以是基本上平面的。可以去除自平坦化隔离材料的一部分，阻挡材料的一部分和导电通孔的突出材料的一部分，以露出导电通路。在暴露阻挡材料的至少一个横向延伸部分之后，可以停止去除自平坦化隔离材料，阻挡材料和导电通孔。

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