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1. 发明授权

US06734080B1 Semiconductor isolation material deposition system and method 失效
标题翻译：半导体隔离材料沉积系统及方法
公开(公告)号：US06734080B1
公开(公告)日：2004-05-11
申请号：US10159078
申请日：2002-05-31
申请人： Nian Yang , John Jianshi Wang , Tien-Chun Yang
发明人： Nian Yang , John Jianshi Wang , Tien-Chun Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A semiconductor isolation material deposition system and method that facilitates convenient and efficient integrated multi-step deposition of isolation regions is presented. In one embodiment of the present invention, an integrated circuit includes densely configured component areas and sparsely configured component areas. An active area in a wafer is created and a shallow trench space is formed. A thin layer of TEOS isolation material layer is deposited on top of the active area and the shallow trench. For example, the layer of thin layer of TEOS isolation material is in a range of 4000 to 5000 angstroms thick over the top of underlying active areas. A reverse mask and pre-planarization etch is performed on the thin layer of TEOS isolation material. The remaining TEOS edge spikes between the densely configured component area and the sparsely configured component area are minimal (e.g., about 500 angstroms. The remaining excess oxidant and silicon nitride are removed utilizing chemical mechanical polishing processes. In one exemplary implementation, the present invention facilitates an integrated approach to STI fabrication processes that achieve successful high yielding results by considering the impacts of one process step on another.
摘要翻译：介绍了半导体隔离材料沉积系统及其方法，便于实现隔离区域的多步沉积。在本发明的一个实施例中，集成电路包括密集配置的组件区域和稀疏配置的组件区域。产生晶片中的有效区域并形成浅沟槽空间。 TEOS隔离材料层的薄层沉积在有源区域和浅沟槽的顶部。例如，薄层的TEOS隔离材料层的厚度在下面有效区域顶部的4000至5000埃的范围内。在TEOS隔离材料的薄层上进行反掩模和预平面化蚀刻。在密集配置的部件区域和稀疏构造的部件区域之间的剩余的TEOS边缘尖峰是最小的（例如，约500埃），使用化学机械抛光工艺去除剩余的多余的氧化剂和氮化硅。在一个示例性实施方式中，通过考虑一个工艺步骤对另一个工艺步骤的影响，可以获得成功的高产量结果的STI制造工艺的综合方法。

2. 发明授权

US06825083B1 Method for reducing shallow trench isolation edge thinning on thin gate oxides to improve peripheral transistor reliability and performance for high performance flash memory devices 有权
标题翻译：用于减少薄栅极氧化物上的浅沟槽隔离边缘薄化的方法，以提高高性能闪存器件的外围晶体管可靠性和性能
公开(公告)号：US06825083B1
公开(公告)日：2004-11-30
申请号：US10126814
申请日：2002-04-19
申请人： Nian Yang , John Jianshi Wang , Xin Guo , Tien-Chun Yang
发明人： Nian Yang , John Jianshi Wang , Xin Guo , Tien-Chun Yang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning for peripheral thin gate transistor devices 480 in an integrated circuit 400 comprising flash memory devices 380, and both thick 390 and thin 480 gate transistor devices. The method begins by forming a tunnel oxide layer 310 over a semiconductor substrate 430 for the formation of the flash memory devices 380 (step 220). A mask 350 is formed over the thin gate transistor devices 480 to inhibit formation of a thick gate oxide layer 360 for the formation of the thick gate transistor devices 390 (step 230). The mask 350 reduces shallow trench isolation (STI) recess by eliminating removal of the thick gate oxide layer 360 before forming a thin oxide layer 410 for the thin gate transistor devices 480.
摘要翻译：一种半导体集成电路制造方法。具体地，本发明的一个实施例公开了一种用于减少硅的浅沟槽隔离（STI）角凹槽的方法，以便在包括闪存器件380的集成电路400中减少外围薄栅晶体管器件480的STI边缘变薄，以及两者厚390和薄型480栅极晶体管器件。该方法开始于在半导体衬底430上形成隧道氧化物层310以形成闪存器件380（步骤220）。掩模350形成在薄栅极晶体管器件480上，以阻止形成厚栅极氧化物层360以形成厚栅极晶体管器件390（步骤230）。掩模350通过在形成用于薄栅极晶体管器件480的薄氧化物层410之前消除厚栅极氧化层360的去除来减少浅沟槽隔离（STI）凹陷。

3. 发明授权

US06717850B1 Efficient method to detect process induced defects in the gate stack of flash memory devices 失效
标题翻译：高效的方法来检测闪存器件的栅极堆叠中的工艺引起的缺陷
公开(公告)号：US06717850B1
公开(公告)日：2004-04-06
申请号：US10313676
申请日：2002-12-05
申请人： Jiang Li , Nian Yang , Zhigang Wang , John Jianshi Wang
发明人： Jiang Li , Nian Yang , Zhigang Wang , John Jianshi Wang
IPC分类号： G11C1604
CPC分类号： G11C29/50 , G11C16/04 , G11C2029/0403
摘要： A method of processing a semiconductor device is disclosed and comprises applying a relatively high voltage across a gate stack of a flash memory cell for a certain period of time. Then, the polarity of the applied voltage is reversed and is again applied across the gate stack for another certain period of time. The voltage applied is greater than a channel erase voltage utilized for the memory cell. This applied voltage causes extrinsic defects to become amplified at interfaces of oxide/insulator layers of the gate stack. Then, the memory cell is tested (e.g., via a battery of tests) in order to determine if the memory cell is defective. If the cell is defective (e.g., fails the test), it can be assumed that substantial extrinsic defects were present in the memory cell and have been amplified resulting in the test failure. If the cell passes the test, it can be assumed that the memory cell is substantially free from extrinsic defects. Defective memory cells/devices can be marked or otherwise indicated as being defective.
摘要翻译：公开了一种处理半导体器件的方法，并且包括在闪存单元的栅极堆叠上施加相当高的电压一段时间。然后，施加的电压的极性反转，并再次施加在栅极堆叠另外一段时间。施加的电压大于用于存储器单元的通道擦除电压。该施加的电压导致外部缺陷在栅极堆叠的氧化物/绝缘体层的界面处被放大。然后，测试存储器单元（例如，通过测试电池），以便确定存储器单元是否有故障。如果细胞有缺陷（例如，测试失败），则可以认为在存储单元中存在大量的外在缺陷并且被放大，导致测试失败。如果单元通过测试，则可以认为存储单元基本上没有外在缺陷。存储器单元/器件不良或可能被标记为有缺陷。

4. 发明授权

US06797650B1 Flash memory devices with oxynitride dielectric as the charge storage media 有权
标题翻译：具有氧氮化物介质的闪存器件作为电荷存储介质
公开(公告)号：US06797650B1
公开(公告)日：2004-09-28
申请号：US10342032
申请日：2003-01-14
申请人： Zhigang Wang , Nian Yang , John Jianshi Wang , Jiang Li
发明人： Zhigang Wang , Nian Yang , John Jianshi Wang , Jiang Li
IPC分类号： H01L2131
CPC分类号： H01L21/28202 , H01L21/28273 , H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/513 , H01L29/518
摘要： One aspect of the invention relates to flash memory device that stores charge in a substantially stoichiometric silicon oxynitride dielectric. A stoichiometric silicon oxynitride dielectric can be represented by the formula (Si3N4)x(SiO2)(1-x), where x is from 0-1. A substantially stoichiometric silicon oxynitride dielectric has relatively few atoms that do not fit into the foregoing formula. The flash memory devices of the present invention have fewer defects and lower leakage than comparable SONOS-type flash memory devices. Another aspect of the invention relates to assessing the stoichiometry by FTIR, refractive index measurement, or a combination of the two.
摘要翻译：本发明的一个方面涉及将电荷存储在基本上化学计量的氮氧化硅电介质中的闪存器件。化学计量的氮氧化硅电介质可由式（Si 3 N 4）x（SiO 2）（1-x）表示，其中x为0-1。基本上化学计量的氮氧化硅电介质具有不符合上述公式的相对较少的原子。本发明的闪速存储器件具有比可比较的SONOS型闪存器件更少的缺陷和更低的泄漏。本发明的另一方面涉及通过FTIR，折射率测量或两者的组合来评估化学计量。

5. 发明授权

US06777957B1 Test structure to measure interlayer dielectric effects and breakdown and detect metal defects in flash memories 失效
标题翻译：用于测量层间电介质效应和击穿并检测闪存中的金属缺陷的测试结构
公开(公告)号：US06777957B1
公开(公告)日：2004-08-17
申请号：US10174734
申请日：2002-06-18
申请人： Nian Yang , Zhigang Wang , John Jianshi Wang
发明人： Nian Yang , Zhigang Wang , John Jianshi Wang
IPC分类号： G01R2726
CPC分类号： H01L27/11521 , G11C16/04 , G11C29/50 , G11C2029/0403 , G11C2029/5002 , H01L22/34 , H01L27/115 , H01L2924/3011
摘要： An apparatus for testing a dielectric property of a material constituting the interlayer dielectric of a flash memory device is formed by a layer (122) of the dielectric material disposed throughout a test structure (200) representative of the flash memory device and a plurality of conductors (117A, 117B, 117C) disposed within that layer (122) or a pair of planar conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509) deposited such that the conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509) are substantially parallel to each other and the layer (122) of dielectric material is disposed throughout a test structure (400, 500) so as to separate the conductors (402, 404; 502, 503; 504, 505; 506, 507; 508, 509), the test structure (400, 500) functioning as a capacitor. The apparatus may also test a conductive property of a material constituting the conducting lines of a flash memory device by disposing a conductor (801, 901) through the dielectric material (122).
摘要翻译：用于测试构成闪速存储器件的层间电介质的材料的介电性能的装置由设置在表示闪速存储器件的测试结构（200）内的介电材料层（122）和多个导体（122A），或者一对平面导体（402,404; 502,503,504,505,506,507,508,509），这些导体（402,404） ; 502,503,504,505,506,507,508,509,506,507,508,505,506,507,508,505,505,505,508,505,509,506,507,508,505,509,508,509,508,509,508,509,505,505,509,508,509,508,509,505,505,509,505,505,509,505,505,509,505,505,509,50 所述测试结构（400,500）用作电容器，所述测试结构（400,500）用作电容器（402,404; 502,503,504,505,506,507,508,509）。该设备还可以通过将电介质材料（122）布置在导体（801,901）上来测试构成闪存器件的导线的材料的导电性能。

6. 发明授权

US06764920B1 Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird's beak formation for high performance flash memory devices 有权
标题翻译：用于使用偏氮化物带和用于高性能闪存器件的小鸟嘴形成来减少隧道氧化物上的浅沟槽隔离边缘薄化的方法
公开(公告)号：US06764920B1
公开(公告)日：2004-07-20
申请号：US10126840
申请日：2002-04-19
申请人： Nian Yang , John Jianshi Wang , Unsoon Kim
发明人： Nian Yang , John Jianshi Wang , Unsoon Kim
IPC分类号： H01L2176
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76224 , H01L21/823481 , H01L29/66825
摘要： A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning on tunnel oxides (510) for flash memories (devices M and N). An STI process is implemented to isolate flash memory devices (devices M and N) in the semiconductor structure (200). In the STI process, a nitride layer (210) is deposited over a silicon substrate (280). An STI region (290) is formed defining STI corners (240) where a top surface (270) of the silicon substrate (280) and the STI region (290) converge. The STI region (290) is filled with an STI field oxide and planarized until reaching the nitride layer (210). A local oxidation of silicon (LOCOS) is then performed to oxidize the top surface (270) of the silicon substrate adjacent to the STI corners (240). Oxidized silicon is grown to boost the thickness of a later formed tunnel oxide layer (510) at the STI corners (240).
摘要翻译：一种半导体集成电路制造方法。具体地，本发明的一个实施例公开了一种用于减少硅的浅沟槽隔离（STI）角凹槽的方法，以便减少闪存（器件M和N）的隧道氧化物（510）上的STI边缘变薄。实施STI处理以隔离半导体结构（200）中的闪存器件（器件M和N）。在STI工艺中，氮化物层（210）沉积在硅衬底（280）上。形成STI区域（290），其限定了硅基板（280）的顶表面（270）和STI区域（290）会聚的STI拐角（240）。 STI区域（290）填充有STI场氧化物并且被平坦化直到到达氮化物层（210）。然后进行硅的局部氧化（LOCOS）以氧化邻近STI拐角（240）的硅衬底的顶表面（270）。生长氧化硅以增强在STI拐角（240）处的稍后形成的隧道氧化物层（510）的厚度。

7. 发明授权

US06590260B1 Memory device having improved programmability 失效
标题翻译：存储器件具有改进的可编程性
公开(公告)号：US06590260B1
公开(公告)日：2003-07-08
申请号：US10103077
申请日：2002-03-20
申请人： Nian Yang , John Jianshi Wang , Zhigang Wang
发明人： Nian Yang , John Jianshi Wang , Zhigang Wang
IPC分类号： H01L2976
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/7883
摘要： A method for enhancing the operating characteristics of memory devices (400C), such as flash memory devices, by manipulating the Fermi energy levels of the substrate (406) and the floating gate (404). In so doing, the gap between the minimum conduction band energy level (408) and the Fermi energy level (412) of the floating gate (404) is extended so as to readily facilitate the movement of electrons from the substrate (406) into the floating gate (404).
摘要翻译：一种用于通过操纵衬底（406）和浮动栅极（404）的费米能级来增强诸如闪存器件的存储器件（400C）的操作特性的方法。在这样做时，浮动栅极（404）的最小导带能量水平（408）和费米能级（412）之间的间隙被延伸，以便容易地促进电子从衬底（406）移动到浮动门（404）。

8. 发明授权

US06784061B1 Process to improve the Vss line formation for high density flash memory and related structure associated therewith 有权
标题翻译：改进用于高密度闪速存储器的Vss线形成及其相关结构的方法
公开(公告)号：US06784061B1
公开(公告)日：2004-08-31
申请号：US10179723
申请日：2002-06-25
申请人： Nian Yang , John Jianshi Wang , Hyeon-Seag Kim
发明人： Nian Yang , John Jianshi Wang , Hyeon-Seag Kim
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/66825
摘要： One aspect of the invention relates to a method of a NOR-type flash memory and associated structure which comprises forming a flash memory array on a semiconductor substrate in a core region of the flash memory. The flash memory array comprises a plurality of flash memory cells which each have a source region and a drain region in the semiconductor substrate. A first portion of a first dielectric layer is formed over the flash memory array, and contact holes in the first dielectric layer are formed down to source regions of flash memory cells in the core region. A trench is then formed in the first dielectric layer and extends between the two contact holes. The contact holes and trench are then filled with a conductive material, thereby electrically coupling together the source regions of the two flash memory cells. A second portion of the first dielectric layer is then formed over the first portion of the first dielectric layer and the trench, thereby embedding the source contacts and trench in within the first dielectric layer.
摘要翻译：本发明的一个方面涉及NOR型闪速存储器及其相关结构的方法，其包括在闪速存储器的核心区域中的半导体衬底上形成闪存阵列。闪存阵列包括多个闪存单元，每个闪存单元在半导体衬底中具有源区和漏区。第一电介质层的第一部分形成在闪速存储器阵列上，并且第一介电层中的接触孔形成为芯区域中的闪存单元的源区。然后在第一介电层中形成沟槽并在两个接触孔之间延伸。然后用导电材料填充接触孔和沟槽，从而将两个闪存单元的源极区域电耦合在一起。然后在第一介电层和沟槽的第一部分上形成第一介电层的第二部分，从而将源极触点和沟槽嵌入第一介电层内。

9. 发明授权

US07505298B2 Transfer of non-associated information on flash memory devices 有权
标题翻译：在闪存设备上传送非相关信息
公开(公告)号：US07505298B2
公开(公告)日：2009-03-17
申请号：US11741996
申请日：2007-04-30
申请人： Nian Yang , Yonggang Wu , Tien-Chun Yang
发明人： Nian Yang , Yonggang Wu , Tien-Chun Yang
IPC分类号： G11C5/06 , G11C7/10
CPC分类号： G11C8/12 , G11C7/12 , G11C7/18 , G11C16/24 , G11C2207/002
摘要： Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit.
摘要翻译：描述了通过存储器阵列在闪速存储器件内传送信息的方式。控制器从存储单元检索信息，然后解码器解码该信息。信息通过一个通过门到一个第二个控制器的一系列位线设置。位线都与存储单元相关联，以及与其他存储单元相关联的位线。一系列晶体管与每个位线相关联。基于如果位线与当前使用的存储单元相关联，不同的晶体管是有效的。

10. 发明申请

US20080136381A1 Method to provide a higher reference voltage at a lower power supply in flash memory devices 有权
标题翻译：在闪存器件中的较低电源处提供较高参考电压的方法
公开(公告)号：US20080136381A1
公开(公告)日：2008-06-12
申请号：US11634776
申请日：2006-12-06
申请人： Tien-Chun Yang , Yonggang Wu , Nian Yang
发明人： Tien-Chun Yang , Yonggang Wu , Nian Yang
IPC分类号： G05F1/10 , G11C5/14
CPC分类号： G11C5/147 , G05F3/08 , G11C16/30
摘要： A fast reference circuit having active feedback includes a bias supply circuit and a variable divider circuit connected by an active feedback path to the bias supply circuit, and a comparator circuit connected to the variable divider circuit, the bias supply circuit, and a reference node of the variable divider circuit. In one embodiment, a start-up circuit initially discharges a potential at the bias supply and comparator circuits, then initializes a reference voltage at the reference node at about zero volts to improve repeatability. In one embodiment, the variable voltage divider comprises an impendence that is trimmed based on a sheet resistance of a process used to fabricate the fast reference circuit, and further comprises a variable reference current circuit coupled to the impedance and configured to generate a current having a value based on a desired reference voltage and to conduct the current through the impedance, thereby generating the reference voltage associated therewith. The comparator circuit is configured to compare the bias supply voltage to the reference voltage, and drive the bias supply and the variable divider circuit in response to the comparison, thereby quickly stabilizing the reference voltage.
摘要翻译：具有有源反馈的快速参考电路包括偏置电源电路和通过有源反馈路径连接到偏置电源电路的可变分频器电路，以及连接到可变分频器电路，偏置电源电路和参考节点的参考节点可变分频电路。在一个实施例中，启动电路首先在偏置电源和比较器电路处放电，然后在约零伏特的参考节点初始化参考电压，以提高可重复性。在一个实施例中，可变分压器包括基于用于制造快速参考电路的工艺的薄层电阻而修整的阻抗，并且还包括耦合到阻抗的可变参考电流电路，并且被配置为产生具有基于所需参考电压的值，并且将电流传导通过阻抗，由此产生与其相关联的参考电压。比较器电路被配置为将偏置电源电压与参考电压进行比较，并且响应于比较来驱动偏置电源和可变分频器电路，由此快速稳定参考电压。

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