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1. 发明授权

US07105383B2 Packaged semiconductor with coated leads and method therefore 有权
标题翻译：具有涂层引线的封装半导体及方法
公开(公告)号：US07105383B2
公开(公告)日：2006-09-12
申请号：US10230743
申请日：2002-08-29
申请人： Nhat D. Vo , Alan H. Woosley
发明人： Nhat D. Vo , Alan H. Woosley
IPC分类号： H01L21/50
CPC分类号： H01L23/49586 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01046 , H01L2924/01079 , H01L2924/181 , H05K3/3426 , Y02P70/613 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor die is housed in a package body. Leads, which are electrically coupled to the semiconductor die, extend from the package body and are for connecting to a printed circuit board or other device. The leads are coated with a material that protects the leads from oxidation. The coating is compatible with solder techniques that are commonly used to attach packaged semiconductors to a printed circuit board. In some examples, the coating is removable, after drying, at temperatures below one hundred eighty degrees Celsius. This allows for solder processes, which are typically at least 180° C., to remove the coating thereby exposing the leads, which has been protected from oxidation, so that it can be soldered to the printed circuit board. In some examples, the coating material includes an organic material. In some examples, the coating material is an organic solderability preservative (OSP).
摘要翻译：半导体管芯被容纳在封装体中。电耦合到半导体管芯的引线从封装体延伸并且用于连接到印刷电路板或其它器件。引线涂有保护引线免受氧化的材料。该涂层与通常用于将封装半导体连接到印刷电路板的焊接技术相容。在一些实例中，涂层在干燥后可在不到108摄氏度的温度下去除。这允许通常至少180℃的焊接工艺去除涂层，从而暴露已被防止氧化的引线，使得其可以焊接到印刷电路板。在一些实例中，涂层材料包括有机材料。在一些实例中，涂层材料是有机可焊性防腐剂（OSP）。

2. 发明申请

US20070267755A1 INTEGRATED CIRCUIT HAVING PADS AND INPUT/OUTPUT (I/O) CELLS 有权
公开(公告)号：US20070267755A1
公开(公告)日：2007-11-22
申请号：US11383653
申请日：2006-05-16
申请人： Nhat D. Vo , Tu-Anh T. Tran , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
发明人： Nhat D. Vo , Tu-Anh T. Tran , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L24/06 , H01L2224/02166 , H01L2224/05093 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01079 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.

3. 发明申请

US20070267748A1 INTEGRATED CIRCUIT HAVING PADS AND INPUT/OUTPUT (I/O) CELLS 审中-公开
标题翻译：具有PADS和INPUT / OUTPUT（I / O）电池的集成电路
公开(公告)号：US20070267748A1
公开(公告)日：2007-11-22
申请号：US11383656
申请日：2006-05-16
申请人： Tu-Anh N. Tran , Nhat D. Vo , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
发明人： Tu-Anh N. Tran , Nhat D. Vo , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/05093 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/06051 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/00014 , H01L2924/00012
摘要： A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.
摘要翻译：垫（20）电连接到第一I / O单元（14），同时物理地覆盖第二I / O单元（16）的有源电路。注意，虽然焊盘（20）覆盖第二I / O单元（16），但是焊盘（20）不与I / O单元（16）电连接。这样的图案可以以任何期望的方式复制，使得I / O单元（例如300-310）可以具有比对应的垫（320-324和330-335）更细的间距。此外，可以不增加I / O单元（132-135）的宽度“c”，可以增加焊盘的尺寸（例如焊盘131可能大于焊盘130）。这种图案（例如500）可以被布置成使得在一个或多个维度中所需的区域可以被最小化。

4. 发明授权

US07808117B2 Integrated circuit having pads and input/output (I/O) cells 有权
标题翻译：集成电路具有焊盘和输入/输出（I / O）单元
公开(公告)号：US07808117B2
公开(公告)日：2010-10-05
申请号：US11383653
申请日：2006-05-16
申请人： Nhat D. Vo , Tu-Anh N. Tran , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
发明人： Nhat D. Vo , Tu-Anh N. Tran , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L2224/02166 , H01L2224/05093 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01079 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.
摘要翻译：垫（20）电连接到第一I / O单元（14），同时物理地覆盖第二I / O单元（16）的有源电路。注意，虽然焊盘（20）覆盖第二I / O单元（16），但是焊盘（20）不与I / O单元（16）电连接。这样的图案可以以任何期望的方式复制，使得I / O单元（例如300-310）可以具有比相应的垫（320-324和330-335）更细的间距。此外，可以增加焊盘的尺寸（例如焊盘131可能大于焊盘130），而不必增加I / O单元（132-135）的宽度“c”。这种图案（例如500）可以被布置成使得在一个或多个维度中所需的区域可以被最小化。

5. 发明授权

US07215014B2 Solderable metal finish for integrated circuit package leads and method for forming 有权
标题翻译：集成电路封装引线的可焊接金属表面和成型方法
公开(公告)号：US07215014B2
公开(公告)日：2007-05-08
申请号：US10901844
申请日：2004-07-29
申请人： Peng Su , Sheila F. Chopin , Nhat D. Vo
发明人： Peng Su , Sheila F. Chopin , Nhat D. Vo
IPC分类号： H01L23/495
CPC分类号： H01L23/49579 , H01L23/49582 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01078 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A packaged integrated circuit includes a die surrounded by an encapsulant in which leads are used to electrically connect the die, which is internal to the encapsulant, externally. The leads have a primary metal that is used for electrical conduction and physical support. The external portion of the lead is coated with another metal, typically tin, that is useful for soldering. This tin layer is formed in a manner that ensures that it is porous. Although porous is generally thought to be a bad characteristic, it turns out to be very effective in absorbing stress and thus retarding whisker growth. Whisker growth, which can short adjacent leads together as well as cause other deleterious effects, has been a major source of failures in packaged integrated circuits. An additional layer of very thin tin that is non-porous can be added before or after the porous tin layer has been deposited.
摘要翻译：封装的集成电路包括由密封剂包围的管芯，其中引线用于将外部封装材料内部的管芯电连接。引线具有用于导电和物理支撑的主金属。引线的外部部分涂覆有可用于焊接的另一种金属（通常为锡）。该锡层以确保其是多孔的方式形成。虽然多孔通常被认为是不良特征，但是在吸收应力并因此阻止晶须生长方面证明是非常有效的。晶须的增长一直是封装集成电路故障的主要原因，它可以将相邻引线连接在一起并引起其他有害影响。可以在沉积多孔锡层之前或之后加入非多孔的非常薄的锡的附加层。

6. 发明授权

US06617524B2 Packaged integrated circuit and method therefor 有权
标题翻译：封装集成电路及其方法
公开(公告)号：US06617524B2
公开(公告)日：2003-09-09
申请号：US10013401
申请日：2001-12-11
申请人： Nhat D. Vo
发明人： Nhat D. Vo
IPC分类号： H05K100
CPC分类号： H01L21/565 , H01L2224/49171
摘要： To mitigate mold encapsulant bleeding and solder mask cracking in plastic semiconductor packages, a damming structure constructed from metal traces is formed in-line with the encapsulant perimeter. In one embodiment, each damming trace is connected to only one electrical trace, which includes a bonding connection, a signal portion and a plating portion. The damming traces can consist of one trace that is wider than any of the signal traces or multiple rows of traces, for example. The result is a reduction in mold encapsulant bleeding and, thus, an eradication of the processes performed to clean the bleeding.
摘要翻译：为了减轻塑料半导体封装中的模具密封剂渗出和焊接掩模开裂，由金属迹线构成的阻塞结构与密封剂周边成一直线。在一个实施例中，每个阻塞迹线仅连接到一个电迹线，其包括接合连接，信号部分和电镀部分。例如，阻挡迹线可以包括比任何信号迹线或多行迹线更宽的一条迹线。结果是模具密封剂渗血减少，因此消除了清洁出血所进行的过程。

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