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1. 发明申请

US20070267748A1 INTEGRATED CIRCUIT HAVING PADS AND INPUT/OUTPUT (I/O) CELLS 审中-公开
标题翻译：具有PADS和INPUT / OUTPUT（I / O）电池的集成电路
公开(公告)号：US20070267748A1
公开(公告)日：2007-11-22
申请号：US11383656
申请日：2006-05-16
申请人： Tu-Anh N. Tran , Nhat D. Vo , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
发明人： Tu-Anh N. Tran , Nhat D. Vo , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/05093 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/06051 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/00014 , H01L2924/00012
摘要： A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.
摘要翻译：垫（20）电连接到第一I / O单元（14），同时物理地覆盖第二I / O单元（16）的有源电路。注意，虽然焊盘（20）覆盖第二I / O单元（16），但是焊盘（20）不与I / O单元（16）电连接。这样的图案可以以任何期望的方式复制，使得I / O单元（例如300-310）可以具有比对应的垫（320-324和330-335）更细的间距。此外，可以不增加I / O单元（132-135）的宽度“c”，可以增加焊盘的尺寸（例如焊盘131可能大于焊盘130）。这种图案（例如500）可以被布置成使得在一个或多个维度中所需的区域可以被最小化。

2. 发明授权

US07808117B2 Integrated circuit having pads and input/output (I/O) cells 有权
标题翻译：集成电路具有焊盘和输入/输出（I / O）单元
公开(公告)号：US07808117B2
公开(公告)日：2010-10-05
申请号：US11383653
申请日：2006-05-16
申请人： Nhat D. Vo , Tu-Anh N. Tran , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
发明人： Nhat D. Vo , Tu-Anh N. Tran , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L2224/02166 , H01L2224/05093 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01079 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.
摘要翻译：垫（20）电连接到第一I / O单元（14），同时物理地覆盖第二I / O单元（16）的有源电路。注意，虽然焊盘（20）覆盖第二I / O单元（16），但是焊盘（20）不与I / O单元（16）电连接。这样的图案可以以任何期望的方式复制，使得I / O单元（例如300-310）可以具有比相应的垫（320-324和330-335）更细的间距。此外，可以增加焊盘的尺寸（例如焊盘131可能大于焊盘130），而不必增加I / O单元（132-135）的宽度“c”。这种图案（例如500）可以被布置成使得在一个或多个维度中所需的区域可以被最小化。

3. 发明申请

US20070267755A1 INTEGRATED CIRCUIT HAVING PADS AND INPUT/OUTPUT (I/O) CELLS 有权
公开(公告)号：US20070267755A1
公开(公告)日：2007-11-22
申请号：US11383653
申请日：2006-05-16
申请人： Nhat D. Vo , Tu-Anh T. Tran , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
发明人： Nhat D. Vo , Tu-Anh T. Tran , Burton J. Carpenter , Dae Y. Hong , James W. Miller , Kendall D. Phillips
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L24/06 , H01L2224/02166 , H01L2224/05093 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01079 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.

4. 发明授权

US08129226B2 Power lead-on-chip ball grid array package 有权
标题翻译：电源引导片上球栅阵列封装
公开(公告)号：US08129226B2
公开(公告)日：2012-03-06
申请号：US12599625
申请日：2007-05-10
申请人： James P. Johnston , Chu-Chung Lee , Tu-Anh N. Tran , James W. Miller , Kevin J. Hess
发明人： James P. Johnston , Chu-Chung Lee , Tu-Anh N. Tran , James W. Miller , Kevin J. Hess
IPC分类号： H01L21/44
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/4951 , H01L23/49833 , H01L23/50 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/91 , H01L2224/24226 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48235 , H01L2224/48471 , H01L2224/49175 , H01L2224/49433 , H01L2224/4945 , H01L2224/85191 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/14 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2224/4554
摘要： A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by using an encapsulated patterned leadframe conductor (59) that is disposed over the die (52) and bonded to a plurality of bonding pads (45) formed in a BGA carrier substrate (42) and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.
摘要翻译：形成诸如球栅阵列封装的封装组件（30），其通过使用设置在模具（52）上的封装的图案化引线框导体（59）来分布跨集成电路管芯（52）的内部区域的电力）并且接合到形成在BGA载体衬底（42）中的多个接合焊盘（45）和内部管芯区域中，从而将内部管芯区域电连接到外部提供的参考电压。

5. 发明申请

US20100270663A1 Power Lead-on-Chip Ball Grid Array Package 有权
标题翻译：电源片内球栅阵列封装
公开(公告)号：US20100270663A1
公开(公告)日：2010-10-28
申请号：US12599625
申请日：2007-05-10
申请人： James P. Johnston , Chu-Chung Lee , Tu-Anh N. Tran , James W. Miller , Kevin J. Hess
发明人： James P. Johnston , Chu-Chung Lee , Tu-Anh N. Tran , James W. Miller , Kevin J. Hess
IPC分类号： H01L23/538 , H01L21/98 , H01L21/50
CPC分类号： H01L23/49816 , H01L23/3128 , H01L23/4951 , H01L23/49833 , H01L23/50 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/91 , H01L2224/24226 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48235 , H01L2224/48471 , H01L2224/49175 , H01L2224/49433 , H01L2224/4945 , H01L2224/85191 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/14 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2224/4554
摘要： A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by using an encapsulated patterned leadframe conductor (59) that is disposed over the die (52) and bonded to a plurality of bonding pads (45) formed in a BGA carrier substrate (42) and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.
摘要翻译：形成诸如球栅阵列封装的封装组件（30），其通过使用设置在模具（52）上的封装的图案化引线框导体（59）来分布跨集成电路管芯（52）的内部区域的电力）并且接合到形成在BGA载体衬底（42）中的多个接合焊盘（45）和内部管芯区域中，从而将内部管芯区域电连接到外部提供的参考电压。

6. 发明申请

US20110020133A1 TORSION BLADE PIVOT WINDMILL 审中-公开
公开(公告)号：US20110020133A1
公开(公告)日：2011-01-27
申请号：US12897048
申请日：2010-10-04
申请人： James W. Miller
发明人： James W. Miller
IPC分类号： F03D1/00
CPC分类号： F03D1/0658 , F03D1/0608 , F05B2240/30 , Y02E10/721 , Y02E10/726
摘要： A pair of airfoil blades having a longitudinal axis coincident with one another. Each blade is bent at the center on the plane of the chord. Each blade has an airfoil tip blade placed at the outer most trailing edge. The blades are affixed by their root ends to opposite ends of a torsion shaft. The blade chords are offset from one another, which defines a blade pitch angle. The torsion shaft is journaled perpendicular through a driveshaft, whereas the rotation of the blades can transfer through the torsion shaft to the driveshaft and cause the driveshaft to turn, eliminating the need for a hub. The blades are adapted to pivot along with the torsion shaft. The blades lie in substantially the same plane, and are adapted for rotation in a plane orthogonal to the longitudinal axis of the driveshaft. Each blade has an airfoil shaped fluid gate valve disposed on the leading edge.
摘要翻译：一对具有彼此重合的纵轴的翼型叶片。每个叶片在和弦平面上的中心弯曲。每个叶片具有放置在最外侧最后缘的翼型末端叶片。叶片的根端固定在扭转轴的相对端。叶片和弦彼此偏移，这限定了叶片桨距角。扭转轴通过驱动轴垂直地轴向旋转，而叶片的旋转可以通过扭转轴传递到驱动轴，并使驱动轴转动，从而无需轮毂。叶片适于与扭转轴一起枢转。叶片位于基本上相同的平面中，并且适于在与驱动轴的纵向轴线正交的平面中旋转。每个叶片具有设置在前缘上的翼型流体闸阀。

7. 发明授权

US07817387B2 MIGFET circuit with ESD protection 有权
标题翻译： MIGFET电路具有ESD保护
公开(公告)号：US07817387B2
公开(公告)日：2010-10-19
申请号：US11971591
申请日：2008-01-09
申请人： Michael G. Khazhinsky , Leo Mathew , James W. Miller
发明人： Michael G. Khazhinsky , Leo Mathew , James W. Miller
IPC分类号： H02H9/00 , H01L23/62
CPC分类号： H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protected circuit is coupled to a power supply voltage rail and includes a multiple independent gate field effect transistor (MIGFET), a pre-driver, and a hot gate bias circuit. The MIGFET has a source/drain path coupled between an output pad and the power supply voltage rail and has a first gate terminal and a second gate terminal. The pre-driver circuit has an output. The hot gate bias circuit is coupled to the first gate terminal of the MIGFET, and the output of the pre-driver circuit is coupled to the second gate terminal of the MIGFET. The hot gate bias circuit is configured to apply a bias voltage to the first gate terminal of the MIGFET during an ESD event that increases the breakdown voltage of the MIGFET so as to better withstand the ESD event.
摘要翻译：静电放电（ESD）保护电路耦合到电源电压轨，并包括多个独立的栅极场效应晶体管（MIGFET），预驱动器和热门偏置电路。 MIGFET具有耦合在输出焊盘和电源电压轨之间的源/漏路径，并且具有第一栅极端子和第二栅极端子。预驱动电路有一个输出。热门偏置电路耦合到MIGFET的第一栅极端子，并且预驱动器电路的输出耦合到MIGFET的第二栅极端子。热门偏置电路被配置为在ESD事件期间向MIGFET的第一栅极端施加偏置电压，这增加了MIGFET的击穿电压，以便更好地承受ESD事件。

8. 发明授权

US07777998B2 Electrostatic discharge circuit and method therefor 有权
标题翻译：静电放电电路及其方法
公开(公告)号：US07777998B2
公开(公告)日：2010-08-17
申请号：US11852396
申请日：2007-09-10
申请人： Michael A. Stockinger , Michael G. Khazhinsky , James W. Miller
发明人： Michael A. Stockinger , Michael G. Khazhinsky , James W. Miller
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0292
摘要： Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.
摘要翻译：集成电路的电路通常包括防静电放电（ESD）事件。除了第一ESD电流路径之外，还可以提供第二ESD电流路径，用于在ESD事件期间使ESD电流远离待保护的电路。除了用于向受保护电路提供电源和接地电压的标准电源和接地总线之外，可以添加一个或多个额外的电源和/或接地总线以及相关联的电路以改善ESD保护。

9. 发明授权

US07593202B2 Electrostatic discharge (ESD) protection circuit for multiple power domain integrated circuit 有权
标题翻译：多功率集成电路的静电放电（ESD）保护电路
公开(公告)号：US07593202B2
公开(公告)日：2009-09-22
申请号：US11264557
申请日：2005-11-01
申请人： Michael G. Khazhinsky , Martin J. Bayer , James W. Miller , Bryan D. Preble
发明人： Michael G. Khazhinsky , Martin J. Bayer , James W. Miller , Bryan D. Preble
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (300/400) includes first and second power domains and a bank of input/output (I/O) cells (305/405) coupled to the first and second power domains. The bank of I/O cells (305/405) includes a first plurality of active clamps (374/445) for the first power domain and a second plurality of active clamps (384/425) for the second power domain wherein the first (374/445) and second (384/425) pluralities of active clamps overlap along the bank of I/O cells. According to one aspect each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving an output signal referenced to a respective first power domain, and at least one ESD protection element (425, 445) for a respective second power domain. According to another aspect, each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving a respective output signal and at least one ESD protection element for each of a first power domain and a second power domain.
摘要翻译：集成电路（300/400）包括耦合到第一和第二电源域的第一和第二电源域和一组输入/输出（I / O）单元（305/405）。 I / O单元组（305/405）包括用于第一功率域的第一多个有源钳位（374/445）和用于第二功率域的第二多个有源钳位（384/425），其中第一（ 374/445）和第二（384/425）个多个有源钳位沿I / O单元组重叠。根据一个方面，多个输入/输出单元（420,440）中的每一个具有用于接收参考相应的第一功率域的输出信号的接合焊盘（421,441）和至少一个ESD保护元件（425,440） 445）用于相应的第二功率域。根据另一方面，多个输入/输出单元（420,440）中的每一个具有用于接收相应输出信号的接合焊盘（421,441）和用于第一功率域和第一功率域中的每一个的至少一个ESD保护元件第二功率域。

10. 发明申请

US20090174973A1 MIGFET CIRCUIT WITH ESD PROTECTION 有权
标题翻译：具有ESD保护功能的MIGFET电路
公开(公告)号：US20090174973A1
公开(公告)日：2009-07-09
申请号：US11971591
申请日：2008-01-09
申请人： Michael G. Khazhinsky , Leo Mathew , James W. Miller
发明人： Michael G. Khazhinsky , Leo Mathew , James W. Miller
IPC分类号： H02H9/04
CPC分类号： H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protected circuit is coupled to a power supply voltage rail and includes a multiple independent gate field effect transistor (MIGFET), a pre-driver, and a hot gate bias circuit. The MIGFET has a source/drain path coupled between an output pad and the power supply voltage rail and has a first gate terminal and a second gate terminal. The pre-driver circuit has an output. The hot gate bias circuit is coupled to the first gate terminal of the MIGFET, and the output of the pre-driver circuit is coupled to the second gate terminal of the MIGFET. The hot gate bias circuit is configured to apply a bias voltage to the first gate terminal of the MIGFET during an ESD event that increases the breakdown voltage of the MIGFET so as to better withstand the ESD event.
摘要翻译：静电放电（ESD）保护电路耦合到电源电压轨，并包括多个独立的栅极场效应晶体管（MIGFET），预驱动器和热门偏置电路。 MIGFET具有耦合在输出焊盘和电源电压轨之间的源/漏路径，并且具有第一栅极端子和第二栅极端子。预驱动电路有一个输出。热门偏置电路耦合到MIGFET的第一栅极端子，并且预驱动器电路的输出耦合到MIGFET的第二栅极端子。热门偏置电路被配置为在ESD事件期间向MIGFET的第一栅极端施加偏置电压，这增加了MIGFET的击穿电压，以便更好地承受ESD事件。

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