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1. 发明授权

US5455831A Frame group transmission and reception for parallel/serial buses 失效
标题翻译：并行/串行总线的帧组发送和接收
公开(公告)号：US5455831A
公开(公告)日：1995-10-03
申请号：US71115
申请日：1993-06-01
申请人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Wescott , Vincent P. Zeyak, Jr.
发明人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Wescott , Vincent P. Zeyak, Jr.
IPC分类号： G06F13/12 , G06F15/17 , G06F15/173 , H04J3/06 , H04L7/10 , H04L29/06 , H04L29/08 , H04L29/14 , G07C1/00
CPC分类号： G06F13/122 , G06F15/17 , G06F15/17343 , H04J3/0629 , H04L29/06 , H04L69/40 , H04L7/10 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. The transceivers for each member of the parallel bus asynchronously achieve synchronism from either end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.
摘要翻译：一种以串行方式跨多个光纤并行传输数据块的系统和方法。帧组被提供为用于在每个光纤上串行发送相关数据并将正在发送的数据结合在一起的机制。帧组不具有序列号，因此，接收机根据各个帧的到达时间确定哪些帧是帧组的一部分。并行总线的每个成员的收发器异步地实现了光纤任一端的同步。因此，消除了对公共时钟的需要。总线两侧的接收机通过对由总线另一侧发射机产生的校准信息执行偏移测量来确定每个导体的相对偏斜度。当从总线两侧看到的所有导体上的歪斜已被确定时，偏差值通过总线交换，从而使发射机能够设置适当的帧间距。

2. 发明授权

US5267240A Frame-group transmission and reception for parallel/serial buses 失效
标题翻译：并行/串行总线的帧组发送和接收
公开(公告)号：US5267240A
公开(公告)日：1993-11-30
申请号：US839986
申请日：1992-02-20
申请人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott , Vincent P. Zeyak, Jr.
发明人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott , Vincent P. Zeyak, Jr.
IPC分类号： H04L29/00 , H04J3/06 , H04L25/02 , H04L29/06 , H04L29/14 , G06K5/04
CPC分类号： H04J3/0629 , H04L69/14 , H04L69/40 , Y02B60/33
摘要： A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

3. 发明授权

US5412803A Communications system having plurality of originator and corresponding recipient buffers with each buffer having three different logical areas for transmitting messages in single transfer 失效
标题翻译：具有多个发起者和对应的接收缓冲器的通信系统，每个缓冲器具有三个不同的逻辑区域，用于在单次传送中发送消息
公开(公告)号：US5412803A
公开(公告)日：1995-05-02
申请号：US839652
申请日：1992-02-20
申请人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
发明人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
IPC分类号： G06F13/00 , G06F13/12 , G06F13/38 , H04L29/06 , H04L29/08 , H04L29/14
CPC分类号： G06F13/122 , H04L69/40 , H04L69/14
摘要： Buffers are provided in two elements between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to. Since the commands must be executed in the sequence in which they are received, a response to the cancel complete command ensures that there are no other cancel operation commands remaining in the receiver, allowing subsequent operations to start without danger of being canceled.
摘要翻译：缓冲器被提供在要传送数据的两个元件中，其中两个缓冲器仅由数据传送的发起者管理。传输消息只需要一次传输，第二次传输确认功能的完成，因为在实现的协议下向接收者传递消息。当发送请求时，在发送方开始一个消息定时器。当接收到请求的正常响应时，定时器被复位; 然而，如果消息操作的持续时间超过超时值，则启动消息超时过程。当取消命令发出时，设置第二个定时器。如果超过此定时器，则可以发出后续取消命令。如果发出后续取消命令，则必须发送取消完成命令并进行响应。由于命令必须按照接收的顺序执行，所以对取消完成命令的响应确保在接收器中不存在其他取消操作命令，允许后续操作开始而不会被取消危险。

4. 发明授权

US5509122A Configurable, recoverable parallel bus 失效
标题翻译：可配置的可并行总线
公开(公告)号：US5509122A
公开(公告)日：1996-04-16
申请号：US71146
申请日：1993-06-01
申请人： Neil G. Bartow , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
发明人： Neil G. Bartow , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
IPC分类号： G06F13/12 , G06F15/17 , G06F15/173 , H04J3/06 , H04L7/10 , H04L29/06 , H04L29/08 , H04L29/14 , G06F11/00
CPC分类号： G06F13/122 , G06F15/17 , G06F15/17343 , H04J3/0629 , H04L29/06 , H04L69/40 , H04L7/10 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors which form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom.
摘要翻译：一种用于在数据处理复合体的元件之间传输信息的系统和用于建立这样的系统的方法。数据处理系统的两个元件通过物理链路连接，该物理链路包括在每个数据处理元件中的通道处附接到收发器的多个导体。一旦收发器已经同步，则交换命令和响应，这确保通道中的所有收发器连接到导体另一端上的相同通道。如果收发器被视为配置，则在配置收发器表中进行条目。搜索允许操作链表，其中包含允许成为操作链接的收发器集合。因此找到的收发器集合与Configured-Transceiver-Table进行比较，以验证集合中的所有成员是否已配置。如果找到一个匹配，这组收发器就成为一个Intended-Operational-Link。验证了目的 - 操作链路，以确保两个通道对形成操作链路的一组导体达成一致。如果“预想 - 运营 - 链路”验证，则建立运营链路。

5. 发明授权

US5357608A Configurable, recoverable parallel bus 失效
标题翻译：可配置的可并行总线
公开(公告)号：US5357608A
公开(公告)日：1994-10-18
申请号：US839657
申请日：1992-02-20
申请人： Neil G. Bartow , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
发明人： Neil G. Bartow , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
IPC分类号： G06F13/00 , G06F15/17 , H04L29/04 , H04L29/06 , H04L29/08 , H04L29/14
CPC分类号： G06F15/17 , H04L29/06 , H04L69/40 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured and an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors will form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom.
摘要翻译：一种用于在数据处理复合体的元件之间传输信息的系统和用于建立这样的系统的方法。数据处理系统的两个元件通过物理链路连接，该物理链路包括在每个数据处理元件中的通道处附接到收发器的多个导体。一旦收发器已经同步，则交换命令和响应，这确保通道中的所有收发器连接到导体另一端上的相同通道。如果收发器被认为是配置的，并且在Configured-Transceiver表中进行了一个条目。搜索允许操作链表，其中包含允许成为操作链接的收发器集合。因此找到的收发器集合与Configured-Transceiver-Table进行比较，以验证集合中的所有成员是否已配置。如果找到一个匹配，这组收发器就成为一个Intended-Operational-Link。验证了目标 - 操作链路，以确保两个通道同意该组导体将形成操作链接。如果“预想 - 运营 - 链路”验证，则建立运营链路。

6. 发明授权

US5598442A Self-timed parallel inter-system data communication channel 失效
标题翻译：自定时并行系统间数据通信通道
公开(公告)号：US5598442A
公开(公告)日：1997-01-28
申请号：US261522
申请日：1994-06-17
申请人： Thomas A. Gregg , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo
发明人： Thomas A. Gregg , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo
IPC分类号： G06F13/42 , H04L7/00 , H04L7/02 , H04L7/033 , H04L7/04 , H04L12/56 , H04L25/14 , H04L25/49 , H04L29/06
CPC分类号： H04L29/06 , G06F13/4278 , H04L25/14 , H04L25/4908 , H04L7/041 , H04L2007/045 , H04L69/14 , H04L7/0008
摘要： A self-timed interface (STI) links two physically separated systems or nodes. A transmit state machine forms each word in a serial bit stream into a plurality of bytes and generates idle and data character sequences. Each byte is separately encoded in a run-length-limited code, along with its idle and data character sequences. Each of the plurality of bytes is transmitted on a separate conducting line along with a transmit clock signal that is also transmitted on a separate line. At the receiver, the data stream on each line is separately phase aligned with the clock, and bit aligned.
摘要翻译：自定义接口（STI）链接两个物理上分离的系统或节点。发送状态机将串行比特流中的每个单词形成多个字节，并生成空闲和数据字符序列。每个字节分别以游程长度限制的代码及其空闲和数据字符序列编码。多个字节中的每一个与分离的线路上发送的发送时钟信号一起在单独的导线上发送。在接收机上，每行上的数据流与时钟分开相位对齐，并且位对齐。

7. 发明授权

US5613068A Method for transferring data between processors on a network by establishing an address space for each processor in each other processor's 失效
标题翻译：通过为每个其他处理器的存储器中的每个处理器建立地址空间来在网络上的处理器之间传送数据的方法
公开(公告)号：US5613068A
公开(公告)日：1997-03-18
申请号：US262081
申请日：1994-06-17
申请人： Thomas A. Gregg , Robert S. Capowski , Frank D. Ferraiolo , Marten J. Halma , Thomas H. Hillock , Robert E. Murray
发明人： Thomas A. Gregg , Robert S. Capowski , Frank D. Ferraiolo , Marten J. Halma , Thomas H. Hillock , Robert E. Murray
IPC分类号： G06F15/16 , G06F13/00 , G06F15/163 , G06F15/167 , G06F15/17 , G06F15/173 , G06F15/177 , H04L12/56 , G06F9/24 , G06F12/08 , G06F13/38
CPC分类号： G06F15/17375 , G06F15/17
摘要： A multi-system interconnect facility in which each central processor complex in the system has an assigned storage space for each other central processor complex in the system for use in communicating with each other central processor complex. The allegiance or association of systems to particular storage spaces is established when each system is initialized and enables a simple interface between user program(s) and message passing hardware consisting primarily of instructions for moving control and data blocks between the program addressable space and the hardware addressable space.
摘要翻译：一种多系统互连设施，其中系统中的每个中央处理器复合体具有用于系统中的每个其他中央处理器复合体的分配的存储空间，用于与彼此中央处理器复合体通信。当每个系统被初始化时，建立系统对特定存储空间的忠诚或关联，并且使得用户程序和消息传递硬件之间的简单接口主要包括用于在程序可寻址空间和硬件之间移动控制和数据块的指令可寻址空间。

8. 发明授权

US5548623A Null words for pacing serial links to driver and receiver speeds 失效
标题翻译：用于将串行链路用于起动和接收速度的空字
公开(公告)号：US5548623A
公开(公告)日：1996-08-20
申请号：US71150
申请日：1993-06-01
申请人： Daniel F. Casper , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
发明人： Daniel F. Casper , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
IPC分类号： G06F13/12 , G06F15/17 , G06F15/173 , H04J3/06 , H04L7/10 , H04L29/06 , H04L29/08 , H04L29/14 , H04L7/00
CPC分类号： G06F13/122 , G06F15/17 , G06F15/17343 , H04J3/0629 , H04L29/06 , H04L69/40 , H04L7/10 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors will form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom. Pacing information is exchanged on the link causing null words to be inserted at an optimum rate to compensate for slow receivers.
摘要翻译：一种用于在数据处理复合体的元件之间传输信息的系统和用于建立这样的系统的方法。数据处理系统的两个元件通过物理链路连接，该物理链路包括在每个数据处理元件中的通道处附接到收发器的多个导体。一旦收发器已经同步，则交换命令和响应，这确保通道中的所有收发器连接到导体另一端上的相同通道。如果收发器被视为配置，则在配置收发器表中进行条目。搜索允许操作链表，其中包含允许成为操作链接的收发器集合。因此找到的收发器集合与Configured-Transceiver-Table进行比较，以验证集合中的所有成员是否已配置。如果找到一个匹配，这组收发器就成为一个Intended-Operational-Link。验证了目标 - 操作链路，以确保两个通道同意该组导体将形成操作链接。如果“预想 - 运营 - 链路”验证，则建立运营链路。在链路上交换起搏信息，导致以最佳速率插入空字来补偿慢速接收机。

9. 发明授权

US5418939A Concurrent maintenance of degraded parallel/serial buses 失效
标题翻译：并行维护降级并行/串行总线
公开(公告)号：US5418939A
公开(公告)日：1995-05-23
申请号：US070587
申请日：1993-06-01
申请人： Kenneth J. Fredericks , Thomas A. Gregg , Paul W. Jones , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott
发明人： Kenneth J. Fredericks , Thomas A. Gregg , Paul W. Jones , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott
IPC分类号： G06F13/12 , G06F15/17 , G06F15/173 , H04J3/06 , H04L7/10 , H04L29/06 , H04L29/08 , H04L29/14 , G06F11/00
CPC分类号： G06F13/122 , G06F15/17 , G06F15/17343 , H04J3/0629 , H04L29/06 , H04L69/40 , H04L7/10 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors will form the operational link. If the Intended-Operation-Link verifies, the operational link is established therefrom.
摘要翻译：一种用于在数据处理复合体的元件之间传输信息的系统和用于建立这样的系统的方法。数据处理系统的两个元件通过物理链路连接，该物理链路包括在每个数据处理元件中的通道处附接到收发器的多个导体。一旦收发器已经同步，则交换命令和响应，这确保通道中的所有收发器连接到导体另一端上的相同通道。如果收发器被视为配置，则在配置收发器表中进行条目。搜索允许操作链表，其中包含允许成为操作链接的收发器集合。因此找到的收发器集合与Configured-Transceiver-Table进行比较，以验证集合中的所有成员是否已配置。如果找到一个匹配，这组收发器就成为一个Intended-Operational-Link。验证了目标 - 操作链路，以确保两个通道同意该组导体将形成操作链接。如果Intended-Operation-Link验证，则建立操作链路。

10. 发明授权

US5455830A Error detection and recovery in parallel/serial buses 失效
标题翻译：并行/串行总线中的错误检测和恢复
公开(公告)号：US5455830A
公开(公告)日：1995-10-03
申请号：US70589
申请日：1993-06-01
申请人： Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
发明人： Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
IPC分类号： G06F13/00 , G06F15/17 , H04L29/04 , H04L29/06 , H04L29/08 , H04L29/14 , G06F15/20 , H04J3/06
CPC分类号： G06F15/17 , H04L29/06 , H04L69/40 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.
摘要翻译：一种以串行方式跨多个光纤并行传输数据块的系统和方法。帧组被提供为用于在每个光纤上串行发送相关数据并将正在发送的数据结合在一起的机制。帧组不具有序列号，因此接收机根据各个帧的到达时间确定哪些帧是帧组的一部分。在一个实施例中，并行总线的每个成员的收发器异步地在光纤的每个端部实现同步。因此，消除了对公共时钟的需要。总线两侧的接收机通过对由总线另一侧发射机产生的校准信息执行偏移测量来确定每个导体的相对偏斜度。当从总线两侧看到的所有导线上的歪斜已被确定时，偏差值在总线上交换，从而使发射机能够设置正确的帧间距。

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