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1. 发明授权

US5613068A Method for transferring data between processors on a network by establishing an address space for each processor in each other processor's 失效
标题翻译：通过为每个其他处理器的存储器中的每个处理器建立地址空间来在网络上的处理器之间传送数据的方法
公开(公告)号：US5613068A
公开(公告)日：1997-03-18
申请号：US262081
申请日：1994-06-17
申请人： Thomas A. Gregg , Robert S. Capowski , Frank D. Ferraiolo , Marten J. Halma , Thomas H. Hillock , Robert E. Murray
发明人： Thomas A. Gregg , Robert S. Capowski , Frank D. Ferraiolo , Marten J. Halma , Thomas H. Hillock , Robert E. Murray
IPC分类号： G06F15/16 , G06F13/00 , G06F15/163 , G06F15/167 , G06F15/17 , G06F15/173 , G06F15/177 , H04L12/56 , G06F9/24 , G06F12/08 , G06F13/38
CPC分类号： G06F15/17375 , G06F15/17
摘要： A multi-system interconnect facility in which each central processor complex in the system has an assigned storage space for each other central processor complex in the system for use in communicating with each other central processor complex. The allegiance or association of systems to particular storage spaces is established when each system is initialized and enables a simple interface between user program(s) and message passing hardware consisting primarily of instructions for moving control and data blocks between the program addressable space and the hardware addressable space.
摘要翻译：一种多系统互连设施，其中系统中的每个中央处理器复合体具有用于系统中的每个其他中央处理器复合体的分配的存储空间，用于与彼此中央处理器复合体通信。当每个系统被初始化时，建立系统对特定存储空间的忠诚或关联，并且使得用户程序和消息传递硬件之间的简单接口主要包括用于在程序可寻址空间和硬件之间移动控制和数据块的指令可寻址空间。

2. 发明授权

US5381535A Data processing control of second-level quest virtual machines without host intervention 失效
标题翻译：二级任务虚拟机的数据处理控制，无需主机干预
公开(公告)号：US5381535A
公开(公告)日：1995-01-10
申请号：US150332
申请日：1993-11-09
申请人： Peter H. Gum , Roger E. Hough , Robert E. Murray
发明人： Peter H. Gum , Roger E. Hough , Robert E. Murray
IPC分类号： G06F9/455 , G06F9/48 , G06F12/00
CPC分类号： G06F9/4843 , G06F9/45558 , G06F2009/45566
摘要： A data processing system operated with multiple levels of virtual machine guests under a host control program. The second level of guests are invoked, operated, and terminated without host intervention, as has been required in prior systems, to significantly increase the operating efficiency of the system. Address translation is done by providing machine capability to translate second level guest addresses to real memory addresses taking advantage of the first level guest being located at a simple offset within real memory. Special facilities for second level guests periodically test for timing interruptions for second level guests and update the second level guest timing facilities.
摘要翻译：一个数据处理系统，在主机控制程序下由多级虚拟机客户端操作。如先前的系统所要求，第二层次的客人被调用，操作和终止，无需主机干预，从而显着提高系统的运行效率。地址转换是通过提供机器能力来将二级客户地址转换为实际存储器地址，利用第一层客户端位于实际存储器内的简单偏移处。第二级客人的特别设施定期测试二级客人的时间间隔，并更新二级宾客时间设施。

3. 发明授权

US5317754A Method and apparatus for enabling an interpretive execution subset 失效
标题翻译：用于启用解释执行子集的方法和装置
公开(公告)号：US5317754A
公开(公告)日：1994-05-31
申请号：US602029
申请日：1990-10-23
申请人： Geoffrey O. Blandy , Lisa C. Heller , Robert E. Murray
发明人： Geoffrey O. Blandy , Lisa C. Heller , Robert E. Murray
IPC分类号： G06F9/48 , G06F12/10 , G06F9/46
CPC分类号： G06F9/4843 , G06F12/1036
摘要： An apparatus and method are established for recognizing guest virtual machines which require only a subset of interpretive execution facilities. The interpretive execution initialization process recognizes subset candidates and bypasses initialization of those facilities not required by the candidates. The candidates are typically short duration jobs and a reduction of initialization and termination overhead creates a substantial performance improvement. The translation lookaside buffer operation is modified to flag subset guest entries as host entries and to associate a unique segment table origin with each subset guest. This allows the TLB entries to remain between guest machine dispatches eliminating TLB purge time and allowing potential reuse of TLB entries if the same guest is repeatedly dispatched within a short time period. The guest machine state description is modified to flag subset candidates based on address translation and timing requirements. Initialization of timing facilities is bypassed in certain subset modes further reducing initialization overhead.
摘要翻译：建立了一种用于识别仅需要解释性执行设施的子集的客体虚拟机的装置和方法。解释执行初始化过程识别子集候选者，并绕过候选人不需要的这些设施的初始化。候选人通常是短期工作，并且初始化和终止开销的减少创造了显着的性能改进。修改翻译后备缓冲区操作被修改为将子组客户条目标记为主机条目，并将唯一段表原点与每个子组客户关联。这允许TLB条目保留在客机调度之间，消除TLB清除时间，并允许在短时间内重复发送同一客户端的TLB条目的潜在重用。根据地址转换和时序要求修改访客机状态描述以标记子集候选。定时设备的初始化在某些子集模式中被绕过，从而进一步降低了初始化开销。

4. 发明授权

US5125091A Object oriented control of real-time processing 失效
标题翻译：面向对象控制的实时处理
公开(公告)号：US5125091A
公开(公告)日：1992-06-23
申请号：US363068
申请日：1989-06-08
申请人： Philip C. Staas, Jr. , Rob Knee , Roy Schilling , Robert E. Murray
发明人： Philip C. Staas, Jr. , Rob Knee , Roy Schilling , Robert E. Murray
IPC分类号： G06Q10/10
CPC分类号： G06Q10/10
摘要： A method of controlling processing in a computer, particularly real-time processing, is performed using computer data objects. Real-time or other input data received from data sources is classified according to pre-stored control data. The control data defines which data source provides the real-time data, how the real-time data is to be processed, where the real-time data is to be stored and what reports the real-time data will be used in. The classified real-time data becomes a computer data object with its associated control data and all subsequent processing is performed on the computer data object.
摘要翻译：使用计算机数据对象来执行控制计算机中的处理，特别是实时处理的方法。根据预先存储的控制数据对从数据源接收的实时或其他输入数据进行分类。控制数据定义哪个数据源提供实时数据，如何处理实时数据，实时数据将被存储在哪里，什么报告实时数据将被使用。分类实时数据成为具有其相关控制数据的计算机数据对象，并且对计算机数据对象执行所有后续处理。

5. 发明授权

US5317705A Apparatus and method for TLB purge reduction in a multi-level machine system 失效
标题翻译：用于多级机器系统中TLB吹扫减少的装置和方法
公开(公告)号：US5317705A
公开(公告)日：1994-05-31
申请号：US112174
申请日：1993-08-26
申请人： Patrick M. Gannon , Peter H. Gum , Roger E. Hough , Robert E. Murray
发明人： Patrick M. Gannon , Peter H. Gum , Roger E. Hough , Robert E. Murray
IPC分类号： G06F12/10 , G06F12/02
CPC分类号： G06F12/1036
摘要： A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB. This time saving results in increased performance in systems with multi-level guests.
摘要翻译：用于减少翻译后备缓冲器（TLB）的清除以减少运行多级虚拟机的系统中的操作系统开销的系统。由于主机或基础客机上的分页活动，每当基础页表项无效时，系统通常必须清除TLB条目。提供了一种用于减少客户转换基于主机页表项的情况的系统。提供附加逻辑来分析每个无效页表项（IPTE）指令，以最小化该指令所需的清除范围。当区域重新定位设施正在运行时，或者当没有构建可页面的TLB时，只需要清除与该页表项对应的条目即可。这种有限的清除通过减少清除时间和地址转换所需的时间来重建TLB来减少开销。节省时间可以提高具有多级客人的系统的性能。

6. 外观设计

USD250960S Desk file 失效
公开(公告)号：USD250960S
公开(公告)日：1979-01-30
申请号：US776954
申请日：1977-03-14
申请人： Kenneth M. Bitner, Jr. , Robert E. Murray , Charles R. Hodges
设计人： Kenneth M. Bitner, Jr. , Robert E. Murray , Charles R. Hodges

7. 发明授权

US06189112B1 Transparent processor sparing 失效
标题翻译：透明处理器备用
公开(公告)号：US06189112B1
公开(公告)日：2001-02-13
申请号：US09070434
申请日：1998-04-30
申请人： Timothy John Slegel , Robert E. Murray
发明人： Timothy John Slegel , Robert E. Murray
IPC分类号： H02H305
CPC分类号： G06F11/2028 , G06F11/2038 , G06F11/2041 , G06F11/2048
摘要： A computer which has multiple central processing units where at least one of the processors is a spare and unused for normal system operation, provides a mechanism for transferring the micro-architected state of a checkstopped processor to a spare processor. Each processor has a set of registers in the central processing unit where the micro-architected state of the processor is kept and these registers are accessible by millicode or microcode running on that processor. A checkstop of a processor is detected by the system, the micro-architected state of that processor is extracted and returned to the system where that state can be loaded into a spare processor in the system and processing resumed without interruption.
摘要翻译：具有多个中央处理单元的计算机，其中至少一个处理器是备用的并且用于正常的系统操作，提供了一种用于将检验处理器的微架构状态传送到备用处理器的机制。每个处理器在中央处理单元中具有一组寄存器，其中处理器的微结构状态被保留，并且这些寄存器可通过在该处理器上运行的微代码或微代码来访问。处理器的检查站由系统检测到，该处理器的微架构状态被提取并返回到系统，其中该状态可以被加载到系统中的备用处理器中，并且处理继续而不中断。

8. 发明授权

US6115829A Computer system with transparent processor sparing 失效
标题翻译：具有透明处理器的计算机系统备用
公开(公告)号：US6115829A
公开(公告)日：2000-09-05
申请号：US70433
申请日：1998-04-30
申请人： Timothy John Slegel , Robert E. Murray
发明人： Timothy John Slegel , Robert E. Murray
IPC分类号： H04B1/74 , H02H3/05 , H03K19/003
CPC分类号： H04B1/74
摘要： A computer which has multiple central processing units where at least one of the processors is a spare and unused for normal system operation, provides a mechanism for transferring the micro-architected state of a checkstopped processor to a spare processor. Each processor has a set of registers in the central processing unit where the micro-architected state of the processor is kept and these registers are accessible by millicode or microcode running on that processor. A checkstop of a processor is detected by the system, the micro-architected state of that processor is extracted and returned to the system where that state can be loaded into a spare processor in the system and processing resumed without interruption.
摘要翻译：具有多个中央处理单元的计算机，其中至少一个处理器是备用的并且用于正常的系统操作，提供了一种用于将检验处理器的微结构化状态传送到备用处理器的机制。每个处理器在中央处理单元中具有一组寄存器，其中处理器的微结构状态被保留，并且这些寄存器可通过在该处理器上运行的微代码或微代码来访问。处理器的检查站由系统检测到，该处理器的微架构状态被提取并返回到系统，其中该状态可以被加载到系统中的备用处理器中，并且处理继续而不中断。

9. 发明授权

US5555414A Multiprocessing system including gating of host I/O and external enablement to guest enablement at polling intervals 失效
标题翻译：多处理系统包括主机I / O的门控和外部启用，以轮询间隔启用客户端
公开(公告)号：US5555414A
公开(公告)日：1996-09-10
申请号：US355566
申请日：1994-12-14
申请人： Roger E. Hough , Robert E. Murray
发明人： Roger E. Hough , Robert E. Murray
IPC分类号： G06F13/24 , G06F13/00
CPC分类号： G06F13/24
摘要： A data processing system operating under a multiprocessing hypervisor program subject to I/O interrupts during a polling interval of the hypervisor program includes one or more processors for executing the hypervisor program and host system and one or more guest systems under the hypervisor program, a storage system connected to the processor's by a bus for storing instructions, data and control information associated with the systems being executed by the processor, the storage system may be partitioned into a number of separate areas each associated with one of the concurrently operating systems, an input/output subsystem for generating I/O interrupts to the processors, apparatus for testing to determine if the system is operating in an interpretive execution mode, apparatus for determining whether a dedicated region facility is active, apparatus for testing whether an I/O enablement mask for a guest system has been set, apparatus for setting a flag if the guest system I/O enablement mask is set, apparatus for testing the flag during each polling interval of the interpretive execution mode, apparatus for loading a control byte from a host control register into a hardware register if the flag has not been set and a count threshold reached, apparatus for testing for host system I/O interrupts and apparatus for switching to the host system if the host system interrupt is present.
摘要翻译：在管理程序的轮询间隔期间受到I / O中断的多处理管理程序操作的数据处理系统包括用于执行管理程序程序和主机系统的一个或多个处理器以及管理程序程序下的一个或多个客户系统，存储器系统通过总线连接到处理器，用于存储与由处理器执行的系统相关联的指令，数据和控制信息，存储系统可以被划分成多个单独的区域，每个区域与并行操作系统之一相关联，输入 /输出子系统，用于产生对处理器的I / O中断，用于测试的装置，用于确定系统是否在解释执行模式下操作;用于确定专用区域设施是否活动的装置，用于测试I / O使能掩模对于客系统已设置，如果客系统I / O启用，则设置标志的设备设置掩码，用于在解释执行模式的每个轮询间隔期间测试标志的装置，用于在没有设置标志并达到计数阈值时将控制字节从主机控制寄存器加载到硬件寄存器的装置，用于测试的装置如果主机系统中断存在，则用于主机系统I / O中断和切换到主机系统的设备。

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