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1. 发明授权

US5267240A Frame-group transmission and reception for parallel/serial buses 失效
标题翻译：并行/串行总线的帧组发送和接收
公开(公告)号：US5267240A
公开(公告)日：1993-11-30
申请号：US839986
申请日：1992-02-20
申请人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott , Vincent P. Zeyak, Jr.
发明人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott , Vincent P. Zeyak, Jr.
IPC分类号： H04L29/00 , H04J3/06 , H04L25/02 , H04L29/06 , H04L29/14 , G06K5/04
CPC分类号： H04J3/0629 , H04L69/14 , H04L69/40 , Y02B60/33
摘要： A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

2. 发明授权

US5455831A Frame group transmission and reception for parallel/serial buses 失效
标题翻译：并行/串行总线的帧组发送和接收
公开(公告)号：US5455831A
公开(公告)日：1995-10-03
申请号：US71115
申请日：1993-06-01
申请人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Wescott , Vincent P. Zeyak, Jr.
发明人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Wescott , Vincent P. Zeyak, Jr.
IPC分类号： G06F13/12 , G06F15/17 , G06F15/173 , H04J3/06 , H04L7/10 , H04L29/06 , H04L29/08 , H04L29/14 , G07C1/00
CPC分类号： G06F13/122 , G06F15/17 , G06F15/17343 , H04J3/0629 , H04L29/06 , H04L69/40 , H04L7/10 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. The transceivers for each member of the parallel bus asynchronously achieve synchronism from either end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.
摘要翻译：一种以串行方式跨多个光纤并行传输数据块的系统和方法。帧组被提供为用于在每个光纤上串行发送相关数据并将正在发送的数据结合在一起的机制。帧组不具有序列号，因此，接收机根据各个帧的到达时间确定哪些帧是帧组的一部分。并行总线的每个成员的收发器异步地实现了光纤任一端的同步。因此，消除了对公共时钟的需要。总线两侧的接收机通过对由总线另一侧发射机产生的校准信息执行偏移测量来确定每个导体的相对偏斜度。当从总线两侧看到的所有导体上的歪斜已被确定时，偏差值通过总线交换，从而使发射机能够设置适当的帧间距。

3. 发明授权

US06279064B1 System and method for loading commands to a bus, directly loading selective commands while queuing and strictly ordering other commands 失效
标题翻译：将命令加载到总线的系统和方法，在排队时直接加载选择性命令，并严格排序其他命令
公开(公告)号：US06279064B1
公开(公告)日：2001-08-21
申请号：US09562274
申请日：2000-04-29
申请人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
发明人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.
摘要翻译：输入/输出总线桥接器和命令排队系统包括外部中断路由器，用于从总线单元控制器（BUC）接收中断命令，并响应中断结束（EOI），中断返回（INR）和中断重发（IRR）命令。中断路由器包括用于排序EOI命令的第一命令队列和用于排序INR和IRR命令的第二命令队列。先进先出（FIFO）命令队列命令总线内存映射输入输出（MMIO）命令。 EOI命令从第一个命令队列指向FIFO命令队列的输入。 EOI命令和MMIO命令从命令队列引导到输入输出总线，INR和IRR命令从第二个命令队列引导到输入输出总线。以这种方式，维护相对于MMIO访问的EOI命令的严格排序，同时允许INR和IRR命令绕过入队的MMIO访问。

4. 发明授权

US06237067B1 System and method for handling storage consistency conflict 失效
标题翻译：处理存储一致性冲突的系统和方法
公开(公告)号：US06237067B1
公开(公告)日：2001-05-22
申请号：US09144763
申请日：1998-08-31
申请人： Raymond J. Eberhard , Eddie Wong , Vincent P. Zeyak, Jr.
发明人： Raymond J. Eberhard , Eddie Wong , Vincent P. Zeyak, Jr.
IPC分类号： G06F1200
CPC分类号： G06F13/1642
摘要： A memory coherency controller. Responsive to a request including a request type and request memory address, relevant queues are examined for queued addresses matching the request memory address. Responsive to a request memory address matching at least one of the queued addresses, the request is rejected. Following a retry latency, the request is retried. When the address of a read request matches queued address in a store queue, at least one request in the store queue is prioritized higher than all other queued requests.
摘要翻译：存储器一致性控制器。响应于包括请求类型和请求存储器地址的请求，检查与请求存储器地址匹配的排队地址的相关队列。响应于与至少一个排队地址匹配的请求存储器地址，该请求被拒绝。在重试延迟之后，将重试该请求。当读请求的地址与存储队列中的排队地址相匹配时，存储队列中的至少一个请求的优先级高于所有其他排队的请求。

5. 发明授权

US6065088A System and method for interrupt command queuing and ordering 失效
公开(公告)号：US6065088A
公开(公告)日：2000-05-16
申请号：US144580
申请日：1998-08-31
申请人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
发明人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
IPC分类号： G06F13/40 , G06F13/24 , G06F13/26
CPC分类号： G06F13/4027
摘要： An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.

6. 发明授权

US06442655B1 System and method for handling storage consistency conflict 有权
标题翻译：处理存储一致性冲突的系统和方法
公开(公告)号：US06442655B1
公开(公告)日：2002-08-27
申请号：US09699957
申请日：2000-10-30
申请人： Raymond J. Eberhard , Eddie Wong , Vincent P. Zeyak, Jr.
发明人： Raymond J. Eberhard , Eddie Wong , Vincent P. Zeyak, Jr.
IPC分类号： G06F1200
CPC分类号： G06F13/1642
摘要： A memory coherency controller. Responsive to a request including a request type and request memory address, relevant queues are examined for queued addresses matching the request memory address. Responsive to a request memory address matching at least one of the queued addresses, the request is rejected. Following a retry latency, the request is retried. When the address of a read request matches queued address in a store queue, at least one request in the store queue is prioritized higher than all other queued requests.
摘要翻译：存储器一致性控制器。响应于包括请求类型和请求存储器地址的请求，检查与请求存储器地址匹配的排队地址的相关队列。响应于与至少一个排队地址匹配的请求存储器地址，该请求被拒绝。在重试延迟之后，将重试该请求。当读请求的地址与存储队列中的排队地址相匹配时，存储队列中的至少一个请求的优先级高于所有其他排队的请求。

7. 发明授权

US06442634B2 System and method for interrupt command queuing and ordering 有权
标题翻译：用于中断命令排队和排序的系统和方法
公开(公告)号：US06442634B2
公开(公告)日：2002-08-27
申请号：US09860309
申请日：2001-05-18
申请人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
发明人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.
摘要翻译：输入/输出总线桥接器和命令排队系统包括外部中断路由器，用于从总线单元控制器（BUC）接收中断命令，并响应中断结束（EOI），中断返回（INR）和中断重发（IRR）命令。中断路由器包括用于排序EOI命令的第一命令队列和用于排序INR和IRR命令的第二命令队列。先进先出（FIFO）命令队列命令总线内存映射输入输出（MMIO）命令。 EOI命令从第一个命令队列指向FIFO命令队列的输入。 EOI命令和MMIO命令从命令队列引导到输入输出总线，INR和IRR命令从第二个命令队列引导到输入输出总线。以这种方式，维护相对于MMIO访问的EOI命令的严格排序，同时允许INR和IRR命令绕过入队的MMIO访问。

8. 发明授权

US6098115A System for reducing storage access latency with accessing main storage and data bus simultaneously 失效
标题翻译：同时访问主存储和数据总线来减少存储访问延迟的系统
公开(公告)号：US6098115A
公开(公告)日：2000-08-01
申请号：US57409
申请日：1998-04-08
申请人： Raymond J. Eberhard , John M. Kaiser, deceased , Warren E. Maule , Eddie Wong , Vincent P. Zeyak, Jr.
发明人： Raymond J. Eberhard , John M. Kaiser, deceased , Warren E. Maule , Eddie Wong , Vincent P. Zeyak, Jr.
IPC分类号： G06F12/08 , G06F13/16 , G06F13/00
CPC分类号： G06F12/0884 , G06F13/161
摘要： System and method reading data from storage by speculatively accessing storage and overlapping data bus access with status determination, thereby reducing storage read access latency. Also, a system and method is provided for reducing storage read access latency by accessing a data bus substantially simultaneously with availability of data from storage. Upon receipt of a storage read request, and before status determination, the requested data is read from storage. Optionally, depending upon bus architecture or the need to minimize control circuitry, control of the data bus may speculatively be sought so that data may be loaded to the data bus upon availability from main storage, still whether or not status has been resolved. Subsequently, if status cancels the read request, further data bus loading is terminated.
摘要翻译：系统和方法通过在状态确定时通过推测访问存储和重叠数据总线访问从存储读取数据，从而减少存储读取访问延迟。而且，提供了一种系统和方法，用于通过基本上同时存储来自数据的可用性同时访问数据总线来减少存储读取访问等待时间。在接收到存储读取请求之后，并且在状态确定之前，从存储器读取所请求的数据。可选地，根据总线架构或最小化控制电路的需要，可以推测性地寻求数据总线的控制，使得可以从主存储器获得可用数据到数据总线上，而不管状态是否已被解决。随后，如果状态取消读取请求，则终止进一步的数据总线加载。

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