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1. 发明申请

US20150200635A1 OPERATIONAL TRANSCONDUCTANCE AMPLIFIER, RECONFIGURABLE FULLY DIFFERENTIAL VOLTAGE SENSING AMPLIFIER AND RECONFIGURABLE FULLY DIFFERENTIAL CAPACITIVE SENSING AMPLIFIER 有权
标题翻译：操作电平放大器，可重新配置的全差分电压感应放大器和可重新配置的全差分电容式感应放大器
公开(公告)号：US20150200635A1
公开(公告)日：2015-07-16
申请号：US14321769
申请日：2014-07-01
申请人： National Taiwan University of Science and Technology
发明人： Tzu-Yun WANG , Min-Rui LAI , Sheng-Yu PENG
IPC分类号： H03F3/45
CPC分类号： H03F1/0272 , H03F1/223 , H03F3/45 , H03F3/45188 , H03F3/45228 , H03F3/45475 , H03F3/45479 , H03F3/4565 , H03F2203/45082 , H03F2203/45292 , H03F2203/45311 , H03F2203/45352 , H03F2203/45404 , H03F2203/45512 , H03F2203/45522 , H03F2203/45528 , H03F2203/45544 , H03F2203/45631
摘要： An operational transconductance amplifier includes a cascode differential-pair amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The cascode differential-pair amplifying circuit is configured for receiving a differential input voltage and for providing a differential output voltage. The bias driving circuit is configured for providing a first bias current to drive the cascode differential-pair amplifying circuit and for adjusting the transconductance of the transconductance amplifier. The bias driving circuit includes a first floating-gate transistor. The first floating-gate transistor is configured for adjusting the first bias current. The common mode feedback circuit is configured for adjusting a second bias current of the cascode differential-pair amplifying circuit according to the differential output voltage so that the differential output voltage is stabilized. A reconfigurable fully differential voltage sensing amplifier and a reconfigurable fully differential capacitive sensing amplifier are disclosed herein as well.
摘要翻译：运算跨导放大器包括共源共栅差分对放大电路，偏置驱动电路和共模反馈电路。共射共栅差分对放大电路被配置为接收差分输入电压并提供差分输出电压。偏置驱动电路被配置为提供第一偏置电流来驱动共源共栅差分对放大电路并用于调节跨导放大器的跨导。偏置驱动电路包括第一浮栅晶体管。第一浮栅晶体管被配置用于调整第一偏置电流。共模反馈电路被配置为根据差分输出电压调整共源共栅差分对放大电路的第二偏置电流，使差分输出电压稳定。本文还公开了可重新配置的全差分电压感测放大器和可重新配置的全差分电容式感测放大器。

2. 发明申请

US20150200648A1 OPERATIONAL TRANSCONDUCTANCE AMPLIFIER, OPERATIONAL TRANSCONDUCTANCE AMPLIFIER-CAPACITOR FILTER AND HIGH ORDER RECONFIGURABLE ANALOG FILTER 有权
标题翻译：运算放大器，运算放大器电容滤波器和高阶可重构模拟滤波器
公开(公告)号：US20150200648A1
公开(公告)日：2015-07-16
申请号：US14453631
申请日：2014-08-07
申请人： National Taiwan University of Science and Technology
发明人： Sheng-Yu PENG , Hung-Yu SHIH , Min-Rui LAI , Chiang-His LEE , Tzu-Yun WANG
IPC分类号： H03H11/04 , H03F1/02 , H03F3/45 , H03H11/12
CPC分类号： H03H11/0422 , H03F1/0205 , H03F1/3211 , H03F3/45183 , H03F3/45237 , H03F3/4565 , H03F2203/45134 , H03F2203/45288 , H03H11/0433 , H03H11/0472
摘要： An operational transconductance amplifier includes a fully-differential amplifying circuit, a bias driving circuit, and a common mode feedback circuit. The fully-differential amplifying circuit is configured for receiving a differential input voltage and providing a differential output voltage. The fully-differential amplifying circuit includes a plurality of diffusor-differential-pair circuits. The bias driving circuit is configured for providing at least one first bias current to drive the fully-differential amplifying circuit and adjust the transconductance of the transconductance amplifier. The common mode feedback circuit is configured for stabilizing the differential output voltage. An operational transconductance amplifier-capacitor (OTA-C) filter and a high order filter are disclosed herein as well.
摘要翻译：运算跨导放大器包括全差分放大电路，偏置驱动电路和共模反馈电路。全差分放大电路被配置为接收差分输入电压并提供差分输出电压。全差分放大电路包括多个扩散差分对电路。偏置驱动电路被配置为提供至少一个第一偏置电流来驱动全差分放大电路并调节跨导放大器的跨导。共模反馈电路被配置为稳定差分输出电压。本文还公开了一种工作跨导放大器 - 电容器（OTA-C）滤波器和高阶滤波器。

3. 发明申请

US20150039802A1 SERIAL-PARALLEL INTERFACE CIRCUIT WITH NONVOLATILE MEMORY 有权
标题翻译：串行并行接口电路与非易失性存储器
公开(公告)号：US20150039802A1
公开(公告)日：2015-02-05
申请号：US14166869
申请日：2014-01-29
申请人： National Taiwan University of Science and Technology
发明人： Sheng-Yu PENG , Chi-An LAI , Chiang-Hsi LEE , Tzu-Yun WANG
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/14 , G11C5/066 , G11C7/10 , G11C16/0433 , G11C2207/107 , G11C2216/10
摘要： A serial-parallel interface circuit with nonvolatile memories is provided. A control module generates a plurality of control signals, wherein the control signals include readout and write-in control signals and memory programming control signals. An input terminal receives a plurality of digital data from external. The digital data are transmitted to the input terminal serially. Memory modules are coupled to the input terminal and receive the control signals from the control module. The input terminal transmits the digital data to the memory modules. One of the memory modules includes a memory unit, and the memory unit stores or transmits one bit of the digital data based on a high voltage control signal and a memory control signal. A plurality of output signal lines are respectively coupled to the memory modules. The memory unit transmits the one bit of the digital data to one of the output signal lines.
摘要翻译：提供一种具有非易失性存储器的串行 - 并行接口电路。控制模块产生多个控制信号，其中控制信号包括读出和写入控制信号和存储器编程控制信号。输入端从外部接收多个数字数据。数字数据被串行传输到输入端。存储器模块耦合到输入端并接收来自控制模块的控制信号。输入端子将数字数据发送到存储器模块。其中一个存储器模块包括存储器单元，并且存储器单元基于高电压控制信号和存储器控制信号存储或发送数字数据的一位。多个输出信号线分别耦合到存储器模块。存储器单元将一位数字数据发送到输出信号线之一。

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