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1. 发明授权

US07181352B2 Method of determining current-voltage characteristics of a device 有权
标题翻译：确定器件的电流 - 电压特性的方法
公开(公告)号：US07181352B2
公开(公告)日：2007-02-20
申请号：US10817764
申请日：2004-04-02
申请人： Natarajan Mahadeva Iyer , Steven Thijs , Vesselin K. Vassilev , Tom Daenen , Vincent De Heyn
发明人： Natarajan Mahadeva Iyer , Steven Thijs , Vesselin K. Vassilev , Tom Daenen , Vincent De Heyn
IPC分类号： G06F19/00
CPC分类号： G01R27/02 , G01R31/002 , G01R31/2632
摘要： A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline. The method may use a rectangular pulse testing set-up, also known as transmission line measurement set-up, with a single loadline characteristic to determine a portion or the complete ESD characteristic of the device-under test.
摘要翻译：用于评估观测到负电阻行为的器件的电流 - 电压特性的方法和系统。更具体地，本发明涉及用于在电压转换区域（正到负）期间准确地评估半导体器件的电应力或ESD性能的方法和系统。该方法包括在脉冲内施加包括至少两个幅度的信号。通过适当地调节第一电平的幅度，使得其足够高以触发待测器件，并且随后在保持被测器件处于导通状态的同一信号中施加一个或多个电平，可以全面提取设备IV特性，而不受系统负载线的限制。该方法可以使用矩形脉冲测试设置，也称为传输线测量设置，具有单个负载线特性以确定被测器件的一部分或完整的ESD特性。

2. 发明授权

US07649722B2 Electrostatic discharge protected circuits 有权
标题翻译：静电放电保护电路
公开(公告)号：US07649722B2
公开(公告)日：2010-01-19
申请号：US11521293
申请日：2006-09-14
申请人： Steven Thijs , Natarajan Mahadeva Iyer , Dimitri Linten
发明人： Steven Thijs , Natarajan Mahadeva Iyer , Dimitri Linten
IPC分类号： H02H9/00 , H02H3/08
CPC分类号： H03F1/223 , H01L27/0251 , H03F1/52 , H03F1/523 , H03F3/191 , H03F3/195 , H03F3/605 , H03F2200/294 , H03F2200/451 , H03F2200/489
摘要： A method for designing an ESD protected analog circuit is described. The method includes creating an analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit as well as a predetermined ESD robustness during an ESD event on the circuit. At least one ESD event is simulated on the analog circuit design to identify at least one weak spot in the circuit. Component-level ESD protection components are added into the analog circuit design around each identified weak spot to reduce failure of the weak spot during an ESD event.
摘要翻译：描述了一种用于设计ESD保护的模拟电路的方法。该方法包括创建模拟电路设计，其包括具有预定电特性的多个互连功能部件和电路级ESD保护部件的模拟电路设计，以在电路的正常操作期间实现预定的模拟性能以及在ESD事件期间预定的ESD稳健性电路。在模拟电路设计中模拟至少一个ESD事件，以识别电路中的至少一个弱点。组件级ESD保护组件被添加到围绕每个识别的弱点的模拟电路设计中，以减少ESD事件期间弱点的故障。

3. 发明申请

US20070058308A1 Electrostatic discharge protected circuits 有权
标题翻译：静电放电保护电路
公开(公告)号：US20070058308A1
公开(公告)日：2007-03-15
申请号：US11521293
申请日：2006-09-14
申请人： Steven Thijs , Natarajan Mahadeva Iyer , Dimitri Linten
发明人： Steven Thijs , Natarajan Mahadeva Iyer , Dimitri Linten
IPC分类号： H02H9/00
CPC分类号： H03F1/223 , H01L27/0251 , H03F1/52 , H03F1/523 , H03F3/191 , H03F3/195 , H03F3/605 , H03F2200/294 , H03F2200/451 , H03F2200/489
摘要： A method for designing an ESD protected analog circuit is described. The method includes creating an analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit as well as a predetermined ESD robustness during an ESD event on the circuit. At least one ESD event is simulated on the analog circuit design to identify at least one weak spot in the circuit. Component-level ESD protection components are added into the analog circuit design around each identified weak spot to reduce failure of the weak spot during an ESD event.
摘要翻译：描述了一种用于设计ESD保护的模拟电路的方法。该方法包括创建模拟电路设计，其包括具有预定电特性的多个互连功能部件和电路级ESD保护部件的模拟电路设计，以在电路的正常操作期间实现预定的模拟性能以及在ESD事件期间预定的ESD稳健性电路。在模拟电路设计中模拟至少一个ESD事件，以识别电路中的至少一个弱点。组件级ESD保护组件被添加到围绕每个识别的弱点的模拟电路设计中，以减少ESD事件期间弱点的故障。

4. 发明申请

US20100142105A1 Bidirectional ESD Power Clamp 审中-公开
标题翻译：双向ESD电源钳位
公开(公告)号：US20100142105A1
公开(公告)日：2010-06-10
申请号：US12630170
申请日：2009-12-03
申请人： Dimitri Linten , Steven Thijs , David Eric Tremouilles , Natarajan Mahadeva Iyer
发明人： Dimitri Linten , Steven Thijs , David Eric Tremouilles , Natarajan Mahadeva Iyer
IPC分类号： H02H9/04
CPC分类号： H01L27/0285
摘要： The disclosed method and device relates to a bidirectional ESD power clamp, comprising a semiconductor structure (BigNFET; BigPFET) having a conductive path connected between first and second nodes and having a triggering node via which the conductive path can be triggered. An ESD transient detection circuit is connected between the first and second nodes and to the triggering node and comprises a first part for detecting an occurrence of a first ESD transient on the first node. The semiconductor structure is provided on an insulator substrate, such that a parasitic conductive path between said first and second nodes via the substrate is avoided. The ESD transient detection circuit further comprises a second part for detecting an occurrence of a second ESD transient on the second node.
摘要翻译：所公开的方法和装置涉及双向ESD功率钳位，其包括半导体结构（BigNFET; BigPFET），其具有连接在第一和第二节点之间的导电路径，并且具有触发节点，通过该触发节点可以触发导电路径。 ESD瞬变检测电路连接在第一和第二节点与触发节点之间，并且包括用于检测第一节点上的第一ESD瞬变的发生的第一部分。半导体结构设置在绝缘体基板上，使得避免了经由基板的所述第一和第二节点之间的寄生导电路径。 ESD瞬态检测电路还包括用于检测第二节点上的第二ESD瞬态的发生的第二部分。

5. 发明授权

US07609076B2 Method of measuring characteristic impedance of electrostatic discharge protecting circuit and apparatus for realizing the same 有权
标题翻译：测量静电放电保护电路的特性阻抗的方法及其实现方法
公开(公告)号：US07609076B2
公开(公告)日：2009-10-27
申请号：US11749912
申请日：2007-05-17
申请人： Toshiyuki Nakaie , Masanori Sawada , Taizo Shintani , Natarajan Mahadeva Iyer , David Eric Tremouilles
发明人： Toshiyuki Nakaie , Masanori Sawada , Taizo Shintani , Natarajan Mahadeva Iyer , David Eric Tremouilles
IPC分类号： G01R27/08
CPC分类号： G01R27/04 , G01R31/2827
摘要： A method of quickly measuring a characteristic impedance of an ESD protecting circuit by applying a discharge voltage to the ESD protecting circuit, includes the steps of measuring a variation in discharge voltage applied to and a variation in discharge current caused to flow through the ESD protecting circuit with time; simultaneously detecting a state when both the discharge voltage and discharge current corresponding to each other are attenuated, after both the discharge voltage and discharge current sequentially rise to arrive individually to respective peak values based on an input to or an output from a computer; and taking a ratio of the variation of discharge voltage to the variation of discharge current during the attenuation as an impedance value when the ratio is nearly constant as well as an apparatus for realizing the same.
摘要翻译：通过向ESD保护电路施加放电电压来快速测量ESD保护电路的特性阻抗的方法包括以下步骤：测量施加的放电电压的变化和通过ESD保护电路流过的放电电流的变化随着时间的推移; 同时检测放电电压和放电电流两者彼此衰减时的状态，在放电电压和放电电流两者依次从计算机输入或从计算机输出之后依次上升到相应的峰值时; 并且当该比率几乎恒定时，将放电电压的变化与衰减期间的放电电流的变化的比率以及实现该比率的装置进行比较。

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