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1. 发明申请

US20090101938A1 Electrostatic Discharge Protection Circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US20090101938A1
公开(公告)日：2009-04-23
申请号：US12345086
申请日：2008-12-29
申请人： Pieter Vanysacker , Benjamin Van Camp , Olivier Marichal , Wybo Geert , Steven Thijs , Gerd Vermont
发明人： Pieter Vanysacker , Benjamin Van Camp , Olivier Marichal , Wybo Geert , Steven Thijs , Gerd Vermont
IPC分类号： H01L29/74 , H01L27/07
CPC分类号： H01L27/0262
摘要： The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.
摘要翻译：本发明提供一种具有多个SCR指（SCR）的可控硅整流器（SCR）的静电放电（ESD）保护电路，其优点是耦合不同的指状物或SCR以减少多触发问题并增加 ESD性能的电路。此外，可以引入升压电路，或者另外可以通过公共基极固有多个SCR耦合。

2. 发明申请

US20110051300A1 Method for Providing Wideband Electrostatic Discharge Protection and Circuits Obtained Therewith 有权
标题翻译：提供宽带静电放电保护和电路的方法
公开(公告)号：US20110051300A1
公开(公告)日：2011-03-03
申请号：US12869444
申请日：2010-08-26
申请人： Steven Thijs , Dimitri Linten
发明人： Steven Thijs , Dimitri Linten
IPC分类号： H02H9/00
CPC分类号： H03F3/607 , H03F1/523
摘要： An distributed electronic circuit (1), such as a transmission line or distributed amplifier, is disclosed comprising an input terminal (2), an output terminal (3), power supply lines (4,5), a sequence of sections (61, 62, 63, 64, 65), between the input terminal (2) and the output terminal (3), arranged to transfer an electrical signal from one section to another section; each section (61, 62, 63, 64, 65) comprising at least one Electro Static Discharge (ESD) protection component (9) configured to, upon occurrence of an ESD event, convey corresponding ESD currents to a power supply line (4, 5); and wherein the ESD components (9) of the respective sections (61, 62, 63, 64, 65) are selected such that, upon occurrence of an ESD event, at least one subsequent section (62, 63, 64, 65) is triggered before the first section (61).
摘要翻译：公开了一种诸如传输线或分布式放大器的分布式电子电路（1），包括输入端（2），输出端（3），电源线（4,5），一段（61，在输入端子（2）和输出端子（3）之间布置成将电信号从一个部分传送到另一个部分; 包括至少一个静电放电（ESD）保护部件（9）的每个部分（61,62,63,64,65），其被配置为在发生ESD事件时将相应的ESD电流传送到电源线（4， 5）; 并且其中选择各个部分（61,62,63,64,65）的ESD部件（9），使得在发生ESD事件时，至少一个后续部分（62,63,64,65）是在第一节之前触发（61）。

3. 发明申请

US20090073621A1 Fast Triggering ESD Protection Device and Method for Designing Same 审中-公开
标题翻译：快速触发ESD保护装置及其设计方法
公开(公告)号：US20090073621A1
公开(公告)日：2009-03-19
申请号：US12209926
申请日：2008-09-12
申请人： Steven Thijs , David Eric Tremouilles
发明人： Steven Thijs , David Eric Tremouilles
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： H01L27/0262 , H01L29/0649 , H01L29/7391 , H01L29/7436 , H01L29/861 , H03K17/08144 , H03K17/305
摘要： A method and apparatus for designing an ESD protection circuit comprising a main ESD device and a triggering device connected to a triggering node of the main ESD device by means of which the main ESD device can be triggered for conducting ESD current at a reduced voltage. The triggering device is located in an initial current path for the ESD current. In this initial current path, there is at least one triggering component which can be triggered from an off-state to an on-state. The triggering speed of this component is considered and its design is optimised in view of increasing its triggering speed. Further shown is an ESD protection circuit in which at least one triggering component is selected to be of a predetermined type for achieving a fast triggering speed, preferably of the gated diode type.
摘要翻译：一种用于设计ESD保护电路的方法和装置，包括主ESD装置和连接到主ESD装置的触发节点的触发装置，通过该ESD触发装置可以触发主ESD装置以在降低的电压下传导ESD电流。触发装置位于用于ESD电流的初始电流路径中。在该初始电流路径中，存在至少一个触发组件，其可以从截止状态触发到导通状态。考虑到该组件的触发速度，考虑到其触发速度的增加，其设计被优化。进一步示出了ESD保护电路，其中至少一个触发组件被选择为预定类型，以实现快速的触发速度，优选地是门控二极管类型。

4. 发明授权

US08508893B2 Method for providing wideband electrostatic discharge protection and circuits obtained therewith 有权
标题翻译：提供宽带静电放电保护的方法及其获得的电路
公开(公告)号：US08508893B2
公开(公告)日：2013-08-13
申请号：US12869444
申请日：2010-08-26
申请人： Steven Thijs , Dimitri Linten
发明人： Steven Thijs , Dimitri Linten
IPC分类号： H02H3/08 , H02H9/02
CPC分类号： H03F3/607 , H03F1/523
摘要： An distributed electronic circuit (1), such as a transmission line or distributed amplifier, is disclosed comprising an input terminal (2), an output terminal (3), power supply lines (4,5), a sequence of sections (61, 62, 63, 64, 65), between the input terminal (2) and the output terminal (3), arranged to transfer an electrical signal from one section to another section; each section (61, 62, 63, 64, 65) comprising at least one Electro Static Discharge (ESD) protection component (9) configured to, upon occurrence of an ESD event, convey corresponding ESD currents to a power supply line (4, 5); and wherein the ESD components (9) of the respective sections (61, 62, 63, 64, 65) are selected such that, upon occurrence of an ESD event, at least one subsequent section (62, 63, 64, 65) is triggered before the first section (61).
摘要翻译：公开了一种诸如传输线或分布式放大器的分布式电子电路（1），包括输入端（2），输出端（3），电源线（4,5），一段（61，在输入端子（2）和输出端子（3）之间布置成将电信号从一个部分传送到另一个部分; 包括至少一个静电放电（ESD）保护部件（9）的每个部分（61,62,63,64,65），其被配置为在发生ESD事件时将相应的ESD电流传送到电源线（4， 5）; 并且其中选择各个部分（61,62,63,64,65）的ESD部件（9），使得在发生ESD事件时，至少一个后续部分（62,63,64,65）是在第一节之前触发（61）。

5. 发明授权

US07821272B2 Method for calibrating an electrostatic discharge tester 有权
标题翻译：校准静电放电测试仪的方法
公开(公告)号：US07821272B2
公开(公告)日：2010-10-26
申请号：US12051749
申请日：2008-03-19
申请人： Mirko Scholz , David Eric Tremouilles , Steven Thijs , Dimitri Linten
发明人： Mirko Scholz , David Eric Tremouilles , Steven Thijs , Dimitri Linten
IPC分类号： G01R35/00 , G01R27/02
CPC分类号： G01R31/002 , G01R35/005
摘要： The present disclosure relates to a method for calibrating transient behaviour of an electrostatic discharge (ESD) test system. The system includes an ESD pulse generator and probe needles for applying a predetermined pulse on a device under test. The probe needles are connected to the ESD pulse generator via conductors. The test system includes measurement equipment for detecting transient behaviour of the device under test by simultaneously capturing voltage and current waveforms the device as a result of the pulse. The method includes the steps of: (a) applying the ESD test system on a first known system with a first known impedance, (b) applying the ESD test system on a second known system with a known second impedance, and (c) determining calibration data for the transient behaviour the ESD test system on the basis of captured voltage and current waveforms, taking into account said known first and second impedances. In preferred embodiments the waveforms are transferred to the frequency domain for correlation.
摘要翻译：本公开涉及一种用于校准静电放电（ESD）测试系统的瞬态特性的方法。该系统包括用于在被测器件上施加预定脉冲的ESD脉冲发生器和探针。探针通过导体连接到ESD脉冲发生器。该测试系统包括用于通过同时捕获脉冲结果的电压和电流波形来检测被测器件的瞬态特性的测量设备。该方法包括以下步骤：（a）将ESD测试系统应用于具有第一已知阻抗的第一已知系统上，（b）将ESD测试系统应用于具有已知第二阻抗的第二已知系统上，以及（c）确定考虑到所述已知的第一和第二阻抗，基于捕获的电压和电流波形，ESD测试系统的瞬态特性的校准数据。在优选实施例中，波形被传送到频域以进行相关。

6. 发明授权

US07649722B2 Electrostatic discharge protected circuits 有权
标题翻译：静电放电保护电路
公开(公告)号：US07649722B2
公开(公告)日：2010-01-19
申请号：US11521293
申请日：2006-09-14
申请人： Steven Thijs , Natarajan Mahadeva Iyer , Dimitri Linten
发明人： Steven Thijs , Natarajan Mahadeva Iyer , Dimitri Linten
IPC分类号： H02H9/00 , H02H3/08
CPC分类号： H03F1/223 , H01L27/0251 , H03F1/52 , H03F1/523 , H03F3/191 , H03F3/195 , H03F3/605 , H03F2200/294 , H03F2200/451 , H03F2200/489
摘要： A method for designing an ESD protected analog circuit is described. The method includes creating an analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit as well as a predetermined ESD robustness during an ESD event on the circuit. At least one ESD event is simulated on the analog circuit design to identify at least one weak spot in the circuit. Component-level ESD protection components are added into the analog circuit design around each identified weak spot to reduce failure of the weak spot during an ESD event.
摘要翻译：描述了一种用于设计ESD保护的模拟电路的方法。该方法包括创建模拟电路设计，其包括具有预定电特性的多个互连功能部件和电路级ESD保护部件的模拟电路设计，以在电路的正常操作期间实现预定的模拟性能以及在ESD事件期间预定的ESD稳健性电路。在模拟电路设计中模拟至少一个ESD事件，以识别电路中的至少一个弱点。组件级ESD保护组件被添加到围绕每个识别的弱点的模拟电路设计中，以减少ESD事件期间弱点的故障。

7. 发明授权

US07181352B2 Method of determining current-voltage characteristics of a device 有权
标题翻译：确定器件的电流 - 电压特性的方法
公开(公告)号：US07181352B2
公开(公告)日：2007-02-20
申请号：US10817764
申请日：2004-04-02
申请人： Natarajan Mahadeva Iyer , Steven Thijs , Vesselin K. Vassilev , Tom Daenen , Vincent De Heyn
发明人： Natarajan Mahadeva Iyer , Steven Thijs , Vesselin K. Vassilev , Tom Daenen , Vincent De Heyn
IPC分类号： G06F19/00
CPC分类号： G01R27/02 , G01R31/002 , G01R31/2632
摘要： A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline. The method may use a rectangular pulse testing set-up, also known as transmission line measurement set-up, with a single loadline characteristic to determine a portion or the complete ESD characteristic of the device-under test.
摘要翻译：用于评估观测到负电阻行为的器件的电流 - 电压特性的方法和系统。更具体地，本发明涉及用于在电压转换区域（正到负）期间准确地评估半导体器件的电应力或ESD性能的方法和系统。该方法包括在脉冲内施加包括至少两个幅度的信号。通过适当地调节第一电平的幅度，使得其足够高以触发待测器件，并且随后在保持被测器件处于导通状态的同一信号中施加一个或多个电平，可以全面提取设备IV特性，而不受系统负载线的限制。该方法可以使用矩形脉冲测试设置，也称为传输线测量设置，具有单个负载线特性以确定被测器件的一部分或完整的ESD特性。

8. 发明申请

US20070002508A1 Electrostatic discharge protection circuit 审中-公开
标题翻译：静电放电保护电路
公开(公告)号：US20070002508A1
公开(公告)日：2007-01-04
申请号：US11395954
申请日：2006-03-30
申请人： Pieter Vanysacker , Benjamin Van Camp , Olivier Marichal , Wybo Geert , Steven Thijs , Gerd Vermont
发明人： Pieter Vanysacker , Benjamin Van Camp , Olivier Marichal , Wybo Geert , Steven Thijs , Gerd Vermont
IPC分类号： H02H9/00
CPC分类号： H01L27/0262
摘要： The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.
摘要翻译：本发明提供一种具有多个SCR指（SCR）的可控硅整流器（SCR）的静电放电（ESD）保护电路，其优点是耦合不同的指状物或SCR以减少多触发问题并增加 ESD性能的电路。此外，可以引入升压电路，或者另外可以通过公共基极固有多个SCR耦合。

9. 发明授权

US08143700B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US08143700B2
公开(公告)日：2012-03-27
申请号：US12345086
申请日：2008-12-29
申请人： Pieter Vanysacker , Benjamin Van Camp , Olivier Marichal , Wybo Geert , Steven Thijs , Gerd Vermont
发明人： Pieter Vanysacker , Benjamin Van Camp , Olivier Marichal , Wybo Geert , Steven Thijs , Gerd Vermont
IPC分类号： H01L27/02
CPC分类号： H01L27/0262
摘要： The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.
摘要翻译：本发明提供一种具有多个SCR指（SCR）的可控硅整流器（SCR）的静电放电（ESD）保护电路，其优点是耦合不同的指状物或SCR以减少多触发问题并增加 ESD性能的电路。此外，可以引入升压电路，或者另外可以通过公共基极固有多个SCR耦合。

10. 发明申请

US20110051301A1 Method for Designing Integrated Electronic Circuits Having Electrostatic Discharge Protection and Circuits Obtained Thereof 审中-公开
标题翻译：设计具有静电放电保护和电路的集成电子电路的方法
公开(公告)号：US20110051301A1
公开(公告)日：2011-03-03
申请号：US12869318
申请日：2010-08-26
申请人： Steven Thijs , Dimitri Linten
发明人： Steven Thijs , Dimitri Linten
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： H01L27/0285
摘要： A method for designing an integrated electronic circuit (1) having Electro Static Discharge (ESD) protection, the method comprising providing an integrated electronic circuit (1) having a predetermined performance during normal operation of the circuit, the integrated electronic circuit (1) comprising a power supply line (2) and at least one active device (4) protected by an ESD protection device (5), the active device (4) being powered from the power supply line (2), simulating an ESD event on the integrated electronic circuit (1) to determine if and where, during the ESD event, a parasitic ESD current path is created between the power supply line (2) and the at least one active device (4), and creating in thus determined parasitic ESD current path a circuit (6) to interrupt this parasitic ESD current path, at least during part of the ESD event.
摘要翻译：一种用于设计具有静电放电（ESD）保护的集成电子电路（1）的方法，所述方法包括提供在电路的正常操作期间具有预定性能的集成电子电路（1），所述集成电子电路（1）包括电源线（2）和由ESD保护装置（5）保护的至少一个有源器件（4），所述有源器件（4）从电源线（2）供电，模拟集成的ESD 电子电路（1），以确定在ESD事件期间是否和何处在电源线（2）和至少一个有源器件（4）之间产生寄生ESD电流路径，并产生如此确定的寄生ESD电流至少在部分ESD事件期间，路径电路（6）中断该寄生ESD电流路径。

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