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1. 发明授权

US06385703B1 Speculative request pointer advance for fast back-to-back reads 有权
标题翻译：用于快速背对背读取的推测请求指针
公开(公告)号：US06385703B1
公开(公告)日：2002-05-07
申请号：US09205647
申请日：1998-12-03
申请人： Narendra S. Khandekar , David D. Lent , Zohar Bogin
发明人： Narendra S. Khandekar , David D. Lent , Zohar Bogin
IPC分类号： G06F1314
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A computer system that includes a host processor (HP), a system memory (SM), and a host bridge coupled to the HP and SM is provided. The host bridge asserts a first read request to the SM and, prior to availability of snoop results in connection with the first read request, the host bridge asserts a following second read request to the SM.
摘要翻译：提供了一种包括主机处理器（HP），系统存储器（SM）和耦合到HP和SM的主机桥的计算机系统。主桥向SM发出第一次读取请求，并且在与第一个读取请求相关的侦听结果的可用性之前，主桥向SM发出以下第二个读取请求。

2. 发明授权

US06243781B1 Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipe 失效
标题翻译：在从出站管道执行发布和未发布的总线事务时，通过将非发布的事务存储在辅助缓冲区中来避免死锁
公开(公告)号：US06243781B1
公开(公告)日：2001-06-05
申请号：US09205051
申请日：1998-12-03
申请人： Wishwesh Gandhi , Tuong Trieu , Ashish Gadagkar , Zohar Bogin , David D. Lent
发明人： Wishwesh Gandhi , Tuong Trieu , Ashish Gadagkar , Zohar Bogin , David D. Lent
IPC分类号： G06F1314
CPC分类号： G06F13/4036
摘要： In a bus resource having an outbound pipe for processing both non-posted and posted transactions in a FIFO manner, a rejected non-posted transaction at the head of the outbound pipe is moved aside and into an auxiliary buffer to avoid a potential blockage of the outbound pipe. The auxiliary buffer is for holding transaction information and return data of the rejected non-posted transaction. The rejected transaction is eventually completed from the auxiliary buffer as determined by an arbiter.
摘要翻译：在具有用于以FIFO方式处理非发布和发布的交易的出站管道的总线资源中，在出站管道的头部处的被拒绝的非贴现事务被移动到辅助缓冲器中，以避免潜在的阻塞出站管道辅助缓冲区用于保存交易信息并返回被拒绝的非贴现交易的数据。被拒绝的事务最终由仲裁器确定的辅助缓冲区完成。

3. 发明授权

US06202112B1 Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge 有权
标题翻译：仲裁方法，以避免跨越桥梁进行交易时的僵局和活锁
公开(公告)号：US06202112B1
公开(公告)日：2001-03-13
申请号：US09205351
申请日：1998-12-03
申请人： Ashish Gadagkar , Zohar Bogin , Narendra Khandekar , David D. Lent
发明人： Ashish Gadagkar , Zohar Bogin , Narendra Khandekar , David D. Lent
IPC分类号： G06F1342
CPC分类号： G06F13/4036
摘要： An embodiment of the invention is directed at a bridge having an outbound pipe for buffering transaction information and data being transported from various devices to a bus. The bridge has an arbiter for granting requests associated with these devices to access the outbound pipe for transferring the transaction information and data into the pipe. The bridge generates a reject signal in response to an initial request associated with an initial transaction from a first one of the devices if the outbound pipe is unavailable to accept further transaction information or data. The bridge has response control logic for generating a retry response for the initial transaction in response to the reject signal. The bridge is able to assert a stamp signal in response to the reject signal. The arbiter in response to the stamp being asserted waits, without granting any other lower priority requests to access the outbound pipe, until a subsequent transaction from the first device makes progress.
摘要翻译：本发明的一个实施例涉及一种具有用于缓冲交易信息和从各种设备传输到总线的数据的出站管的桥。桥接器具有用于授予与这些设备相关联的请求的仲裁器以访问出站管道，用于将事务信息和数据传送到管道中。如果出站管道不可用于接受进一步的交易信息或数据，则桥接器响应于与来自第一设备的初始事务相关联的初始请求生成拒绝信号。桥接器具有用于响应于拒绝信号而产生用于初始事务的重试响应的响应控制逻辑。桥接器能够响应于拒绝信号来声明印记信号。响应于该邮票被断言的仲裁者等待，而不允许任何其他较低优先级的请求访问出站管道，直到来自第一个设备的后续事务进行。

4. 发明授权

US06314472B1 Abort of DRAM read ahead when PCI read multiple has ended 失效
标题翻译：当PCI读取多个已经结束时，DRAM的中止被读取
公开(公告)号：US06314472B1
公开(公告)日：2001-11-06
申请号：US09203127
申请日：1998-12-01
申请人： Tuong P. Trieu , David D. Lent , Ashish S. Gadagkar , Vincent E. VonBokern , Zohar Bogin
发明人： Tuong P. Trieu , David D. Lent , Ashish S. Gadagkar , Vincent E. VonBokern , Zohar Bogin
IPC分类号： G06F300
CPC分类号： G06F13/161
摘要： A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.
摘要翻译：提供计算机系统。计算机系统包括主机处理器（HP），系统存储器（SM）以及输入/输出（I / O）主设备，以执行对SM的连续数据流的读取。计算机系统还包括耦合到HP，SM和I / O主设备的桥。当I / O主设备从SM读取连续的数据流时，桥接器向前读取SM。响应于I / O主设备的脱离接口，桥接器在对SM进行访问提交之前中止对SM的预读访问。

5. 发明授权

US06237055B1 Avoiding livelock when performing a long stream of transactions 失效
标题翻译：执行长时间的事务时避免活动锁定
公开(公告)号：US06237055B1
公开(公告)日：2001-05-22
申请号：US09205024
申请日：1998-12-03
申请人： Tuong Trieu , David D. Lent , Zohar Bogin , Ashish Gadagkar
发明人： Tuong Trieu , David D. Lent , Zohar Bogin , Ashish Gadagkar
IPC分类号： G06F13362
CPC分类号： G06F13/364
摘要： An arbiter comprising logic circuitry configured to delay granting bus ownership to an agent X in response to receiving a first signal which indicates that a device coupled to the bus is not available to service transactions directed at the device over the bus. For instance, the device may be a bridge and the grant is delayed if an inbound pipe of the bridge is full. The arbiter may provide a borrowed grant to an outbound pipe of the device for performing a transaction on the bus while waiting for an inbound pipe of the device to become available.
摘要翻译：一种仲裁器，包括逻辑电路，其被配置为响应于接收到指示耦合到总线的设备不能用于通过总线对设备进行服务的事务的第一信号来延迟向代理X授予总线所有权。例如，如果桥的入站管道已满，则设备可能是桥接器，并且延迟许可。仲裁器可以向设备的出站管道提供借用的授权，用于在等待设备的入站管道变得可用时在总线上进行交易。

6. 发明授权

US5794070A Method and apparatus for fast DMA transfer on an industry standard architecture (ISA) bus 失效
标题翻译：用于工业标准架构（ISA）总线上快速DMA传输的方法和装置
公开(公告)号：US5794070A
公开(公告)日：1998-08-11
申请号：US730777
申请日：1996-10-16
申请人： Jeffrey L. Rabe , Dave Smyth , David D. Lent , Sathyamurthi Sadhasivan , Dahmane Dahmani , Stephen T. Rowland , James S. Coke , Mitchell W. Dale
发明人： Jeffrey L. Rabe , Dave Smyth , David D. Lent , Sathyamurthi Sadhasivan , Dahmane Dahmani , Stephen T. Rowland , James S. Coke , Mitchell W. Dale
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer. The DMA controller and the bus controller also generate a three-clock cycle DMA transfer.
摘要翻译：计算机系统包括直接存储器访问（DMA）传送单元和通过外部总线耦合的多个DMA设备。 DMA传送单元为多个DMA设备实现DMA传输。 DMA传输单元包含DMA控制器，总线仲裁器和总线控制器。 DMA控制器和总线控制器产生一个两个时钟周期的DMA传输。为了实现双时钟周期DMA传输，请求的DMA设备与DMA控制器建立DMA传输，使得在第一时钟周期期间断言DACK＃信号。在第二个时钟周期内，DMA控制器设置存储器地址。在第三个时钟周期内，总线控制器转换外部总线上的命令信号。在断言命令信号时，有效数据在外部总线上被断言。对于需求和块模式操作，在两个时钟周期的DMA传输中执行额外的DMA传输。 DMA控制器和总线控制器也产生三个时钟周期的DMA传输。

7. 发明授权

US5611054A Method and apparatus for decoding and recoding of addresses 失效
标题翻译：地址解码和重新编码的方法和装置
公开(公告)号：US5611054A
公开(公告)日：1997-03-11
申请号：US567405
申请日：1995-12-05
申请人： David D. Lent , Daniel J. Dunn
发明人： David D. Lent , Daniel J. Dunn
IPC分类号： G06F12/02 , H04L29/06 , G06F13/00
CPC分类号： G06F12/0292 , H04L29/06 , H04L69/08
摘要： A semiconductor component is described which directs transmission of data. The component comprises of a decoder device coupled to said first memory device capable of decoding an address of said data in said first format using said stored address in said first memory device. The component also comprises a translator device coupled to said second memory device capable of transmitting said address of said data in said second format corresponding to said address of said data in said first format, wherein the second format contains the same amount of information as the first format.
摘要翻译：描述了指导数据传输的半导体部件。该组件包括耦合到所述第一存储设备的解码器设备，其能够使用所述第一存储设备中的所述存储地址来解码所述第一格式的所述数据的地址。该组件还包括耦合到所述第二存储器装置的转换器装置，其能够以与所述第一格式的所述数据的所述地址对应的所述第二格式的所述数据的所述地址发送，其中所述第二格式包含与所述第一格式相同的信息量格式。

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