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1. 发明授权

US4389281A Method of planarizing silicon dioxide in semiconductor devices 失效
标题翻译：在半导体器件中平面化二氧化硅的方法
公开(公告)号：US4389281A
公开(公告)日：1983-06-21
申请号：US217077
申请日：1980-12-16
申请人： Narasipur G. Anantha , Harsaran S. Bhatia , John S. Lechaton , James L. Walsh
发明人： Narasipur G. Anantha , Harsaran S. Bhatia , John S. Lechaton , James L. Walsh
IPC分类号： C01B33/12 , H01L21/302 , H01L21/3065 , H01L21/3105 , H01L21/311 , H01L21/312 , H01L21/76 , H01L21/306 , C03C15/00
CPC分类号： H01L21/31055 , H01L21/31116 , H01L21/312
摘要： The present invention provides a method for planarizing a non-uniform thickness of oxide, for example silicon dioxide as is formed over oxide-filled trenches used in deep dielectric isolation in integrated circuits. The oxide is removed by a planarizing resist-etching process so that etching in thicker resist areas proceeds at a rate slower than etching in thinner resist areas. A referred etchant is HF gas and etching is preferably at an elevated temperature.
摘要翻译：本发明提供了一种平面化不均匀厚度的氧化物的方法，例如在集成电路中用于深介电隔离的氧化物填充沟槽上形成的二氧化硅。通过平面化抗蚀剂蚀刻工艺去除氧化物，使得较厚抗蚀剂区域中的蚀刻以比较薄的抗蚀剂区域中的蚀刻速率慢。所谓蚀刻剂是HF气体，蚀刻优选处于升高的温度。

2. 发明授权

US4535531A Method and resulting structure for selective multiple base width transistor structures 失效
标题翻译：选择性多基宽度晶体管结构的方法和结果
公开(公告)号：US4535531A
公开(公告)日：1985-08-20
申请号：US360730
申请日：1982-03-22
申请人： Harsaran S. Bhatia , Jack A. Dorler , Santosh P. Gaur , John S. Lechaton , Joseph M. Mosley , Gurumakonda R. Srinivasan
发明人： Harsaran S. Bhatia , Jack A. Dorler , Santosh P. Gaur , John S. Lechaton , Joseph M. Mosley , Gurumakonda R. Srinivasan
IPC分类号： H01L29/73 , H01L21/3065 , H01L21/331 , H01L21/822 , H01L21/8222 , H01L27/04 , H01L27/082 , H01L29/10 , H01L21/82
CPC分类号： H01L27/0825 , H01L21/3065 , H01L21/8222 , H01L29/1004
摘要： A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization.
摘要翻译：描述了一种方法，其允许在集成电路芯片的选定区域中制造非常窄的基极宽度双极晶体管，并且在同一集成电路芯片的其它选定区域上制造宽基极宽度的双极晶体管。将晶体管特性从集成电路芯片的一个区域选择性地变化到另一个区域的能力提供了有价值的集成电路设计的自由度。使用常规技术将集成电路芯片上的双极晶体管加工成发射点形成点。但是，在发射极形成之前，将使用反应离子蚀刻干法蚀刻作为具有非常窄的基极晶体管的选定区域的发射极的基极区域。将其中具有发射极开口的现有氮化硅/二氧化硅层用作该反应离子蚀刻程序的蚀刻掩模。一旦蚀刻完成到期望的深度，则恢复正常处理以形成发射器和金属化的其余部分。

3. 发明授权

US4960726A BiCMOS process 失效
标题翻译： BiCMOS工艺
公开(公告)号：US4960726A
公开(公告)日：1990-10-02
申请号：US424363
申请日：1989-10-19
申请人： John S. Lechaton , Dominic J. Schepis
发明人： John S. Lechaton , Dominic J. Schepis
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/732
CPC分类号： H01L21/8249
摘要： A method for manufacturing a BiCMOS device includes providing a semiconductor substrate including first and second electrically isolated device regions. A layer of insulating material is formed over the first device region, and a layer of conductive material is formed conformally over the device. Portions of the conductive layer are removed to leave a base contact on the surface of the second device region and an insulated gate contact over the surface of the first device region. A FET is formed in the first device region having a channel under the insulated gate. A vertical bipolar transistor is formed in the second device region having a base region contacting the base contact.
摘要翻译：一种制造BiCMOS器件的方法包括提供包括第一和第二电隔离器件区域的半导体衬底。在第一器件区域上形成一层绝缘材料，并且一层导电材料在该器件上保形地形成。去除导电层的部分以在第二器件区域的表面上留下基极接触，并且在第一器件区域的表面上形成绝缘栅极接触。在具有在绝缘栅极下方的沟道的第一器件区域中形成FET。在具有接触基极触点的基极区域的第二器件区域中形成垂直双极晶体管。

4. 发明授权

US08360006B2 Cat litter box liner with an absorbent scratch resistant pad 有权
标题翻译：带有吸收性防刮垫的猫砂纸衬里
公开(公告)号：US08360006B2
公开(公告)日：2013-01-29
申请号：US13066610
申请日：2011-04-19
申请人： John S. Lechaton , Marie Lechaton
发明人： John S. Lechaton , Marie Lechaton
IPC分类号： A01K29/00
CPC分类号： A01K1/0107 , A01K15/024
摘要： A first embodiment of this invention is a cat litter bag composed of a thin plastic bag having a scratch resistant surface on the upper surface to avoid being damaged when used by cats. The scratch resistant material also serves to absorb cat urine to minimize odor during use. By a second embodiment the cat litter bag is shown filled with clean litter for convenience and travel.
摘要翻译：本发明的第一个实施方案是一种猫垫，其由在上表面具有抗划伤表面的薄塑料袋组成，以避免在猫使用时被损坏。耐擦伤材料还用于吸收猫尿，以在使用过程中使气味最小化。在第二个实施例中，为了方便和旅行，猫垫被示出填充有干净的垫料。

5. 发明授权

US4029562A Forming feedthrough connections for multi-level interconnections metallurgy systems 失效
标题翻译：形成多级互连冶金系统的馈通连接
公开(公告)号：US4029562A
公开(公告)日：1977-06-14
申请号：US681367
申请日：1976-04-29
申请人： Bai-Cwo Feng , John S. Lechaton
发明人： Bai-Cwo Feng , John S. Lechaton
IPC分类号： H01L21/3205 , H01L21/28 , H01L21/306 , H01L21/768 , H01L23/522 , C23C15/00
CPC分类号： H01L21/768 , H01L21/7688 , H01L21/76885 , H01L23/5226 , H01L2924/0002
摘要： A method for forming feedthrough connections, or via studs, between levels of metallization atop semiconductor substrates. A first level conductive pattern is formed atop the substrate. A feedthrough pattern is then formed atop the first conductive pattern, the feedthrough pattern including one or more metal studs and a second, expendable material disposed on the studs. The formation of the feedthrough pattern is preferably accomplished by a lift-off process. The expendable material is removable by an etchant which does not substantially attack either the metal or the substrate. An insulator is deposited atop the substrate and the pattern by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the insulator, thereby covering the exposed substrate surfaces and the expendable material but leaving the side surfaces of the material exposed. The expendable material is then etched with said etchant, thereby removing the second material and the portion of the insulator disposed thereon. A second conductive pattern may then be formed atop the insulator and selectively connected to the feedthroughs which thereby provide the interconnection between the first and second levels.
摘要翻译：一种用于在半导体衬底顶部的金属化层之间形成馈通连接或经由螺柱的方法。第一级导电图案形成在衬底上。然后在第一导电图案的顶部形成馈通图案，馈通图案包括一个或多个金属螺柱和设置在螺柱上的第二个可消耗材料。馈通图案的形成优选通过剥离过程来实现。消耗性材料可以通过基本上不侵蚀金属或基材的蚀刻剂来除去。绝缘体通过RF溅射沉积在基板顶部和图案上，该偏压足够高以导致绝缘体的大量再次发射，从而覆盖暴露的基板表面和消耗材料，但是使材料的侧表面露出。然后用所述蚀刻剂蚀刻消耗性材料，从而去除第二材料和设置在其上的绝缘体的部分。然后可以在绝缘体顶上形成第二导电图案，并且选择性地连接到馈通，从而提供第一和第二电平之间的互连。

6. 发明授权

US4502913A Total dielectric isolation for integrated circuits 失效
标题翻译：集成电路的全介电隔离
公开(公告)号：US4502913A
公开(公告)日：1985-03-05
申请号：US393932
申请日：1982-06-30
申请人： John S. Lechaton , Shashi D. Malaviya , Dominic J. Schepis , Gurumakonda R. Srinivasan
发明人： John S. Lechaton , Shashi D. Malaviya , Dominic J. Schepis , Gurumakonda R. Srinivasan
IPC分类号： H01L27/00 , H01L21/3065 , H01L21/316 , H01L21/76 , H01L21/762 , H01L21/763 , H01L21/306 , B44C1/22 , C03C15/00 , H01L27/04
CPC分类号： H01L21/3065 , H01L21/76232 , H01L21/763
摘要： A fully isolated dielectric structure for isolating regions of monocrystalline silicon from one another and method for making such structure are described. The structure uses a combination of recessed oxide isolation with pairs of parallel, anisotropic etched trenches which are subsequently oxidized and filled to give complete dielectric isolation for regions of monocrystalline silicon. The anisotropic etching preferably etches a buried N+ sublayer under the monocrystalline silicon region and then the trench structure is thermally oxidized to consume the remaining N+ layer under the monocrystalline region and to fully isolate the monocrystalline silicon region between pairs of such trenches.
摘要翻译：描述了用于将单晶硅的区域彼此隔离的完全隔离的电介质结构和用于制造这种结构的方法。该结构使用凹陷氧化物隔离与成对的各向异性蚀刻沟槽的组合，其随后被氧化和填充，以为单晶硅区域提供完全介电隔离。各向异性蚀刻优选蚀刻在单晶硅区域下方的掩埋的N +子层，然后将该沟槽结构热氧化以消耗单晶区域下面的剩余N +层，并且在这种沟槽对之间完全隔离单晶硅区域。

7. 发明授权

US4035276A Making coplanar layers of thin films 失效
标题翻译：制作共面层薄膜
公开(公告)号：US4035276A
公开(公告)日：1977-07-12
申请号：US681380
申请日：1976-04-29
申请人： Janos Havas , John S. Lechaton , Joseph Skinner Logan
发明人： Janos Havas , John S. Lechaton , Joseph Skinner Logan
IPC分类号： H05K3/46 , H01L21/027 , H01L21/28 , H01L21/306 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/84 , H01L23/522 , H05K3/14 , C23C15/00
CPC分类号： H01L21/768 , H01L21/0272 , H01L21/312 , H01L21/7688 , H01L21/76885 , H01L21/84 , H01L23/522 , H01L2924/0002 , H05K3/143 , Y10S438/951 , Y10T428/24777
摘要： A method for forming coplanar thin films, particularly conductor-insulator patterns, on a substrate. A pattern which includes a first thin film and an expendable material deposited thereon is formed on the substrate. The expendable material is selected so that it can be selectively removed by an etchant which does not attack the first thin film or an insulator which is to be deposited. The second thin film is deposited by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the second film. This results in the covering of the exposed substrate surfaces and the upper surface of the material with the second film but leaving the side surfaces of the material exposed. The expendable material is then chemically etched so as to lift-off both the material and the second film deposited thereon, thereby leaving a coplanar pattern of first and second thin films.In the preferred embodiment, the first thin film is a conductor and the RF sputtered second thin film is an insulator such as glass. Alternatively, the first thin film could be the insulator with the RF sputtered second film being the conductor, or both thin films could be dissimilar metals or insulators. Via hole studs, or feedthroughs, which are metallic interconnections between a first level conductive pattern (metallization) and a second level conductive pattern, may be formed by repeating substantially the same steps atop the first conductive pattern at desired locations. As many substantially coplanar levels as desired may be formed without the need for etching the second thin film.
摘要翻译：在基板上形成共面薄膜，特别是导体 - 绝缘体图案的方法。在基板上形成包括第一薄膜和沉积在其上的消耗材料的图案。选择消耗材料，使得其可以通过不侵蚀第一薄膜的蚀刻剂或要沉积的绝缘体来选择性地去除。通过RF溅射以足够高的偏压沉积第二薄膜以引起第二膜的显着再次释放。这导致用第二膜覆盖暴露的基板表面和材料的上表面，但是使材料的侧表面暴露。然后对消耗材料进行化学蚀刻，以便剥离沉积在其上的材料和第二膜，由此留下第一和第二薄膜的共面图案。

8. 发明授权

US5086016A Method of making semiconductor device contact including transition metal-compound dopant source 失效
标题翻译：制造包括过渡金属化合物掺杂剂源的半导体器件接触的方法
公开(公告)号：US5086016A
公开(公告)日：1992-02-04
申请号：US606632
申请日：1990-10-31
申请人： Stephen B. Brodsky , Rajiv V. Joshi , John S. Lechaton , James G. Ryan , Dominic J. Schepis
发明人： Stephen B. Brodsky , Rajiv V. Joshi , John S. Lechaton , James G. Ryan , Dominic J. Schepis
IPC分类号： H01L21/225 , H01L21/28 , H01L21/285 , H01L21/331 , H01L21/60
CPC分类号： H01L21/76897 , H01L21/2254 , H01L21/28568 , H01L29/66272 , Y10S148/034 , Y10S148/035
摘要： A contact is provided in a self-aligned manner to a doped region a semiconductor substrate by first forming a layer of a transition metal-boride compound over a selected region on the substrate. A layer of a transition metal-nitride compound is formed over the layer of transition metal-boride compound, and the structure is heated to drive dopant from the layer of transition metal-boride compound into the substrate. The transition metal-boride/transition metal nitride layers are patterned to leave a contact to the doped region.

9. 发明授权

US4752817A High performance integrated circuit having modified extrinsic base 失效
标题翻译：具有改进的外在基极的高性能集成电路
公开(公告)号：US4752817A
公开(公告)日：1988-06-21
申请号：US920920
申请日：1986-10-21
申请人： John S. Lechaton , Philip M. Pitner , Gurumakonda R. Srinivasan
发明人： John S. Lechaton , Philip M. Pitner , Gurumakonda R. Srinivasan
IPC分类号： H01L29/10 , H01L29/732 , H01L29/72
CPC分类号： H01L29/1004 , H01L29/7325
摘要： There is described a process for making a high performance NPN bipolar transistor functioning in a current switch logic circuit. A bipolar transistor is formed within an isolated region of a monocrystalline silicon body wherein the transistor includes an N+ subcollector, an N+ collector reach-through which connects the subcollector to a major surface of the silicon body, a P base region above the subcollector and adjacent to the reach-through region, an N+ emitter region within the base region and extending from the major surface. The base region includes an intrinsic base region located below the emitter region and an extrinsic region located extending from the major surface and adjacent to the emitter region. The extrinsic base preferrably completely surrounds or rings the emitter region. A mask is formed above the major surface and the mask has openings therein only in the areas above major portions of the extrinsic base regions. A P+ type region is formed in the extrinsic base region by ion implanting with a P type dopant to a depth of less than the depth of the N emitter region followed by a short thermal anneal to activate the P dopant. Electrical ohmic contacts are made to the elements of the transistor and the elements are connected in a current switch logic circuit. The use of the high conductivity P+ region in the extrinsic base region closely adjacent to the emitter substantially reduces the extrinsic base resistance. Since the extrinsic base region resistance is reduced, it is possible to reduce the size of the emitter area. Independent doping in the extrinsic base through the mask openings also allows independent control of the intrinsic and extrinsic base resistances. The result of these changes substantially increase the performance of bipolar transistor integrated circuits for current switch logic applications.
摘要翻译：描述了在电流开关逻辑电路中使高性能NPN双极晶体管工作的过程。双极晶体管形成在单晶硅体的隔离区域内，其中晶体管包括N +子集电极，将子集电极连接到硅主体表面的N +集电极通孔，在子集电极之上的P基极区域和相邻的到达通过区域内的基极区域内的N +发射极区域并且从主表面延伸。基极区域包括位于发射极区域下方的本征基极区域和从主表面延伸并邻近发射极区域的非本征区域。外部基极优选地完全围绕或环绕发射极区域。在主表面上形成掩模，并且掩模仅在外部基极区的主要部分上方的区域中具有开口。通过用P型掺杂剂离子注入到低于N发射极区域深度的深度，然后进行短热退火以激活P掺杂剂，在外部基极区域中形成P +型区域。对欧姆晶体元件进行电欧姆接触，元件连接在电流开关逻辑电路中。在与发射极紧密相邻的外部基极区域中使用高电导率P +区域基本上降低了外部基极电阻。由于外部基极区电阻降低，因此能够减小发射极面积的大小。通过掩模开口在外部基极中的独立掺杂也允许独立控制固有和非本征基极电阻。这些变化的结果大大提高了用于电流开关逻辑应用的双极晶体管集成电路的性能。

10. 发明授权

US4090006A Structure for making coplanar layers of thin films 失效
标题翻译：制造共面层薄膜的结构
公开(公告)号：US4090006A
公开(公告)日：1978-05-16
申请号：US781246
申请日：1977-03-25
申请人： Janos Havas , John S. Lechaton , Skinner Logan
发明人： Janos Havas , John S. Lechaton , Skinner Logan
IPC分类号： H05K3/46 , H01L21/027 , H01L21/28 , H01L21/306 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/84 , H01L23/522 , H05K3/14 , C23C15/00
CPC分类号： H01L21/768 , H01L21/0272 , H01L21/312 , H01L21/7688 , H01L21/76885 , H01L21/84 , H01L23/522 , H01L2924/0002 , H05K3/143 , Y10S438/951 , Y10T428/24777
摘要： A method for forming coplanar thin films, particularly conductor-insulator patterns, on a substrate. A pattern which includes a first thin film and an expendable material deposited thereon is formed on the substrate. The expendable material is selected so that it can be selectively removed by an etchant which does not attack the first thin film or an insulator which is to be deposited. The second thin film is deposited by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the second film. This results in the covering of the exposed substrate surfaces and the upper surface of the material with the second film but leaving the side surfaces of the material exposed. The expendable material is then chemically etched so as to lift-off both the material and the second film deposited thereon, thereby leaving a coplanar pattern of first and second thin films.In the preferred embodiment, the first thin film is a conductor and the RF sputtered second thin film is an insulator such as glass. Alternatively, the first thin film could be the insulator with the RF sputtered second film being the conductor, or both thin films could be dissimilar metals or insulators.
摘要翻译：在基板上形成共面薄膜，特别是导体 - 绝缘体图案的方法。在基板上形成包括第一薄膜和沉积在其上的消耗材料的图案。选择消耗材料，使得其可以通过不侵蚀第一薄膜的蚀刻剂或要沉积的绝缘体来选择性地去除。通过RF溅射以足够高的偏压沉积第二薄膜以引起第二膜的显着再次释放。这导致用第二膜覆盖暴露的基板表面和材料的上表面，但是使材料的侧表面暴露。然后对消耗材料进行化学蚀刻，以便剥离沉积在其上的材料和第二膜，由此留下第一和第二薄膜的共面图案。

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