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1. 发明授权

US08304824B2 Semiconductor device comprising buried word lines 有权
标题翻译：包括掩埋字线的半导体器件
公开(公告)号：US08304824B2
公开(公告)日：2012-11-06
申请号：US12719493
申请日：2010-03-08
申请人： Hui-Jung Kim , Yong-Chul Oh , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Hui-Jung Kim , Yong-Chul Oh , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10817 , H01L27/10885 , H01L29/4236
摘要： A semiconductor device includes: an isolation layer for defining a plurality of active areas of a substrate, where the isolation layer is disposed on the substrate; a plurality of buried word lines having upper surfaces that are lower than the upper surfaces of the active areas, being surrounded by the active areas, and extending in a first direction parallel to a main surface of the substrate; a gate dielectric film interposed between the buried word lines and the active areas; and a plurality of buried bit lines having upper surfaces that are lower than the upper surfaces of the plurality of buried word lines and extending parallel to the main surface of the substrate in a second direction that differs from the first direction.
摘要翻译：半导体器件包括：用于限定衬底的多个有源区的隔离层，其中隔离层设置在衬底上; 具有比有源区域的上表面低的上表面的多个掩埋字线被有源区域包围，并且沿与基板的主表面平行的第一方向延伸; 介于掩埋字线和有源区之间的栅介质膜; 以及多个掩埋位线，其具有比所述多个掩埋字线的上表面低的上表面，并且在与所述第一方向不同的第二方向上平行于所述基板的主表面延伸。

2. 发明授权

US08105904B2 Method of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08105904B2
公开(公告)日：2012-01-31
申请号：US12704233
申请日：2010-02-11
申请人： Yong-Chul Oh , Kang-Uk Kim
发明人： Yong-Chul Oh , Kang-Uk Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L27/10876 , H01L27/10885 , H01L27/10894
摘要： A semiconductor device includes an insulation layer disposed on a substrate having a first area and a second area, a first wiring disposed on the insulation layer in the first area, a first active structure disposed on the first wiring, a first gate insulation layer enclosing the first upper portion, a first gate electrode disposed on the first gate insulation layer, a first impurity region disposed at the first lower portion, and a second impurity region disposed at the first upper portion. The first wiring may extend in a first direction. The first active structure includes a first lower portion extending in the first direction and a first upper portion protruding from the first lower portion. The first gate electrode may extend in a second direction. The first impurity region may be electrically connected to the first wiring.
摘要翻译：半导体器件包括设置在具有第一区域和第二区域的衬底上的绝缘层，设置在第一区域中的绝缘层上的第一布线，设置在第一布线上的第一有源结构，第一栅极绝缘层，第一上部，设置在第一栅极绝缘层上的第一栅极电极，设置在第一下部的第一杂质区域和设置在第一上部的第二杂质区域。第一布线可以沿第一方向延伸。第一主动结构包括沿第一方向延伸的第一下部部分和从第一下部部分突出的第一上部部分。第一栅电极可以在第二方向上延伸。第一杂质区域可以电连接到第一布线。

3. 发明授权

US08058683B2 Access device having vertical channel and related semiconductor device and a method of fabricating the access device 有权
标题翻译：具有垂直沟道和相关半导体器件的存取装置及其制造方法
公开(公告)号：US08058683B2
公开(公告)日：2011-11-15
申请号：US11954135
申请日：2007-12-11
申请人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung
发明人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung
IPC分类号： H01L27/088 , H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/823487 , H01L21/84 , H01L27/10823 , H01L27/10885 , H01L29/42392 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate dielectric disposed on the channel, and a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the unified gate electrode/connection line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.
摘要翻译：公开了一种存取装置和半导体装置。进入装置包括分隔下部源极/漏极区域和上部源极/漏极区域的垂直取向的沟道，设置在沟道上的栅极电介质以及耦合到穿过栅极电介质的沟道的统一的栅电极/连接线，其中，统一的栅极电极/连接线包括靠近栅极电介质设置并覆盖下部源极/漏极区域的至少一部分的下降的唇部。

4. 发明授权

US07833864B2 Method of doping polysilicon layer that utilizes gate insulation layer to prevent diffusion of ion implanted impurities into underlying semiconductor substrate 有权
标题翻译：掺杂多晶硅层的方法，其利用栅极绝缘层以防止离子注入的杂质扩散到下面的半导体衬底中
公开(公告)号：US07833864B2
公开(公告)日：2010-11-16
申请号：US11738620
申请日：2007-04-23
申请人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
发明人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
IPC分类号： H01L21/8234
CPC分类号： H01L21/823878 , H01L21/28185 , H01L21/28202 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/513 , H01L29/518
摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
摘要翻译：实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极地区。实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

5. 发明授权

US07737512B2 Integrated circuit devices having uniform silicide junctions 有权
标题翻译：具有均匀硅化物结的集成电路器件
公开(公告)号：US07737512B2
公开(公告)日：2010-06-15
申请号：US11853361
申请日：2007-09-11
申请人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
发明人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
IPC分类号： H01L31/119
CPC分类号： H01L29/41783 , H01L21/28247 , H01L21/28518 , H01L21/823418 , H01L27/105 , H01L27/10873 , H01L27/10894 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.
摘要翻译：提供集成电路器件，其包括集成电路衬底和集成电路衬底上的栅极。门有侧壁。阻挡层间隔件设置在栅极的侧壁上。阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。在从栅极的侧壁突出的阻挡层隔离物的部分上提供硅化物层。

6. 发明申请

US20100084710A1 Capacitor-Less Dynamic Random Access Memory (DRAM) Devices 审中-公开
标题翻译：无电容动态随机存取存储器（DRAM）器件
公开(公告)号：US20100084710A1
公开(公告)日：2010-04-08
申请号：US12564533
申请日：2009-09-22
申请人： Sung-hwan Kim , Yong-chul Oh , Hoon Jeong , Sung-in Hong , Yong-Iack Choi , Ho-ju Song
发明人： Sung-hwan Kim , Yong-chul Oh , Hoon Jeong , Sung-in Hong , Yong-Iack Choi , Ho-ju Song
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/76895 , H01L27/0207 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/10888 , H01L29/7841
摘要： Dynamic random access memory (DRAM) devices including an insulating layer on a semiconductor substrate; a silicon layer on the insulating layer; an active region in the silicon layer; and a unit cell of a transistor on the active region are provided. The DRAM device does not include a capacitor.
摘要翻译：包括半导体衬底上的绝缘层的动态随机存取存储器（DRAM）器件; 绝缘层上的硅层; 硅层中的有源区; 并且提供有源区上的晶体管的单元。 DRAM器件不包括电容器。

7. 发明申请

US20090250736A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090250736A1
公开(公告)日：2009-10-08
申请号：US12385433
申请日：2009-04-08
申请人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L29/94 , H01L29/78
CPC分类号： H01L27/0688 , H01L21/8221
摘要： In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.
摘要翻译：在半导体器件和相关方法中，半导体器件包括衬底，衬底上的绝缘层，绝缘层上的导电结构，导电结构包括至少一种金属硅化物膜图案，导电结构上的半导体图案，所述半导体图案从所述导电结构向上突出，栅电极至少部分地封装所述半导体图案，所述栅电极与所述导电结构间隔开，所述半导体图案的下部的第一杂质区域和所述第二杂质区域在半导体图案的上部。

8. 发明申请

US20080179693A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20080179693A1
公开(公告)日：2008-07-31
申请号：US12014370
申请日：2008-01-15
申请人： Hui-Jung Kim , Jae-Man Yoon , Yong-Chul Oh , Hyun-Woo Chung
发明人： Hui-Jung Kim , Jae-Man Yoon , Yong-Chul Oh , Hyun-Woo Chung
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes a first active pattern protruding from a substrate, a second active pattern on the first active pattern, a gate electrode enclosing a sidewall of the second active pattern, a conductive layer pattern on the first active pattern, a first impurity region in the first active pattern, and a second impurity region at a surface portion of the second active pattern. The first active pattern extending along a predetermined direction may have a first region and a second region. The second active pattern may have a pillar structure and the conductive layer pattern may include a metal or a metal compound.
摘要翻译：半导体器件包括从衬底突出的第一有源图案，第一有源图案上的第二有源图案，封闭第二有源图案的侧壁的栅极电极，第一有源图案上的导电层图案，第一有源图案上的第一杂质区域第一有源图案和第二有源图案的表面部分处的第二杂质区域。沿着预定方向延伸的第一有源图案可以具有第一区域和第二区域。第二活性图案可以具有柱结构，并且导电层图案可以包括金属或金属化合物。

9. 发明授权

US07329927B2 Integrated circuit devices having uniform silicide junctions 有权
标题翻译：具有均匀硅化物结的集成电路器件
公开(公告)号：US07329927B2
公开(公告)日：2008-02-12
申请号：US11166979
申请日：2005-06-24
申请人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
发明人： Se-myeong Jang , Gyo-young Jin , Yong-chul Oh , Hyun-chang Kim
IPC分类号： H01L31/119
CPC分类号： H01L29/41783 , H01L21/28247 , H01L21/28518 , H01L21/823418 , H01L27/105 , H01L27/10873 , H01L27/10894 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.
摘要翻译：提供集成电路器件，其包括集成电路衬底和集成电路衬底上的栅极。门有侧壁。阻挡层间隔件设置在栅极的侧壁上。阻挡层间隔物的一部分从栅极的侧壁突出，暴露出面向集成电路基板的阻挡层隔离物的下表面。在从栅极的侧壁突出的阻挡层隔离物的部分上提供硅化物层。

10. 发明授权

US07307008B2 Methods of forming integrated circuit devices including a multi-layer poly film cell pad contact hole 失效
标题翻译：形成集成电路器件的方法包括多层多晶硅电池垫接触孔
公开(公告)号：US07307008B2
公开(公告)日：2007-12-11
申请号：US10622915
申请日：2003-07-18
申请人： Yong-Chul Oh , Gyo-Young Jin
发明人： Yong-Chul Oh , Gyo-Young Jin
IPC分类号： H01L21/425
CPC分类号： H01L21/76897 , H01L21/76895
摘要： Methods of forming a cell pad contact hole on an integrated circuit include forming adjacent gates on an integrated circuit substrate having a source/drain region extending between the gates. Gate spacers are formed on facing sidewalls of the adjacent gates. A cell pad contact hole is formed aligned to the gates and gate spacers that exposes the source/drain region in the integrated circuit substrate. A first poly film is formed in the cell pad contact hole. An ion region is formed in the source/drain region by ion-implanting through the first poly film and a second poly film is formed on the first poly film that substantially fills the cell pad contact hole.
摘要翻译：在集成电路上形成单元焊盘接触孔的方法包括在集成电路基板上形成相邻栅极，该集成电路基板具有在栅极之间延伸的源极/漏极区域。栅极间隔物形成在相邻栅极的相对侧壁上。形成与栅极和栅极间隔物对准的电池垫接触孔，其暴露集成电路基板中的源极/漏极区域。在电池垫接触孔中形成第一多晶膜。通过离子注入第一多晶硅膜，在源极/漏极区域中形成离子区，而在第一多晶膜上形成基本上填充电池垫接触孔的第二多晶硅膜。

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