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1. 发明申请

US20120299090A1 Semiconductor Devices Including Dual Gate Electrode Structures And Related Methods 有权
标题翻译：包括双栅电极结构的半导体器件及相关方法
公开(公告)号：US20120299090A1
公开(公告)日：2012-11-29
申请号：US13298644
申请日：2011-11-17
申请人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
发明人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
IPC分类号： H01L29/78
CPC分类号： G11C11/4096 , G11C11/404 , G11C11/4085 , H01L21/823437 , H01L27/10823 , H01L27/10873 , H01L27/10876 , H01L27/10891 , H01L27/10894 , H01L29/41741 , H01L29/4236 , H01L29/66484 , H01L29/66613 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.
摘要翻译：半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。此外，第一和第二栅电极可以是电隔离的。还讨论了相关设备，结构，操作方法和制造方法。

2. 发明授权

US08884340B2 Semiconductor devices including dual gate electrode structures and related methods 有权
标题翻译：包括双栅电极结构和相关方法的半导体器件
公开(公告)号：US08884340B2
公开(公告)日：2014-11-11
申请号：US13298644
申请日：2011-11-17
申请人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
发明人： Ji-Young Kim , Gyo-Young Jin , Hyeong-Sun Hong , Yong-Chul Oh , Yoo-Sang Hwang , Sung-Kwan Choi , Dong-Soo Woo , Hyun-Woo Chung
IPC分类号： H01L21/336 , H01L29/772 , G11C11/404 , H01L27/108 , H01L29/66 , H01L29/78 , G11C11/408 , H01L29/417 , H01L29/423 , H01L21/8234
CPC分类号： G11C11/4096 , G11C11/404 , G11C11/4085 , H01L21/823437 , H01L27/10823 , H01L27/10873 , H01L27/10876 , H01L27/10891 , H01L27/10894 , H01L29/41741 , H01L29/4236 , H01L29/66484 , H01L29/66613 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.
摘要翻译：半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。此外，第一和第二栅电极可以是电隔离的。还讨论了相关设备，结构，操作方法和制造方法。

3. 发明申请

US20130288472A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING BURIED CHANNEL ARRAY 有权
标题翻译：制作带通道阵列的半导体器件的方法
公开(公告)号：US20130288472A1
公开(公告)日：2013-10-31
申请号：US13761376
申请日：2013-02-07
申请人： Jay-Bok Choi , Yoo-Sang Hwang , Ah-Young Kim , Ye-Ro Lee , Gyo-Young Jin , Hyeong-sun Hong
发明人： Jay-Bok Choi , Yoo-Sang Hwang , Ah-Young Kim , Ye-Ro Lee , Gyo-Young Jin , Hyeong-sun Hong
IPC分类号： H01L29/423
CPC分类号： H01L29/42312 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L29/4236 , H01L29/66621
摘要： A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.
摘要翻译：制造半导体器件的方法包括在衬底中形成第一和第二平行场区域，所述平行场区域沿第一方向延伸，在形成的第一和第二栅极沟槽中形成第一和第二栅极覆盖层在基板中分别去除栅极覆盖层，使得第一着陆焊盘孔被扩展以部分地覆盖掩埋在衬底中的栅极覆盖层，在第一空间中形成层叠焊盘材料层，并形成位线接触层通过将着陆垫材料层平坦化到覆盖层的顶表面的水平面。

4. 发明授权

US09276074B2 Methods of fabricating semiconductor devices having buried channel array 有权
标题翻译：制造具有掩埋沟道阵列的半导体器件的方法
公开(公告)号：US09276074B2
公开(公告)日：2016-03-01
申请号：US13761376
申请日：2013-02-07
申请人： Jay-Bok Choi , Yoo-Sang Hwang , Ah-Young Kim , Ye-Ro Lee , Gyo-Young Jin , Hyeong-sun Hong
发明人： Jay-Bok Choi , Yoo-Sang Hwang , Ah-Young Kim , Ye-Ro Lee , Gyo-Young Jin , Hyeong-sun Hong
IPC分类号： H01L21/44 , H01L21/336 , H01L29/423 , H01L29/66 , H01L27/108 , H01L27/02
CPC分类号： H01L29/42312 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L29/4236 , H01L29/66621
摘要： A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.
摘要翻译：制造半导体器件的方法包括在衬底中形成第一和第二平行场区域，所述平行场区域沿第一方向延伸，在形成的第一和第二栅极沟槽中形成第一和第二栅极覆盖层在基板中分别去除栅极覆盖层，使得第一着陆焊盘孔被扩展以部分地覆盖掩埋在衬底中的栅极覆盖层，在第一空间中形成层叠焊盘材料层，并形成位线接触层通过将着陆垫材料层平坦化到覆盖层的顶表面的水平面。

5. 发明授权

US08742493B2 Semiconductor devices having vertical channel transistors and methods for fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体器件及其制造方法
公开(公告)号：US08742493B2
公开(公告)日：2014-06-03
申请号：US13285263
申请日：2011-10-31
申请人： Dae-Ik Kim , Hyeong-Sun Hong , Yoo-Sang Hwang , Hyun-Woo Chung
发明人： Dae-Ik Kim , Hyeong-Sun Hong , Yoo-Sang Hwang , Hyun-Woo Chung
IPC分类号： H01L27/108
CPC分类号： H01L29/7827 , H01L27/10876 , H01L29/1033 , H01L29/1087 , H01L29/66666 , H01L29/7831
摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.
摘要翻译：半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

6. 发明申请

US20120119286A1 SEMICONDUCTOR DEVICES HAVING VERTICAL CHANNEL TRANSISTORS AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有垂直通道晶体管的半导体器件及其制造方法
公开(公告)号：US20120119286A1
公开(公告)日：2012-05-17
申请号：US13285263
申请日：2011-10-31
申请人： Dae-Ik Kim , Hyeong-Sun Hong , Yoo-Sang Hwang , Hyun-Woo Chung
发明人： Dae-Ik Kim , Hyeong-Sun Hong , Yoo-Sang Hwang , Hyun-Woo Chung
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L27/10876 , H01L29/1033 , H01L29/1087 , H01L29/66666 , H01L29/7831
摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.
摘要翻译：半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

7. 发明授权

US09601420B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US09601420B2
公开(公告)日：2017-03-21
申请号：US14018709
申请日：2013-09-05
申请人： Yoo-Sang Hwang , Hyun-Woo Chung , Dae-Ik Kim
发明人： Yoo-Sang Hwang , Hyun-Woo Chung , Dae-Ik Kim
IPC分类号： H01L21/768 , H01L23/498 , H01L23/522 , H01L27/108 , H01L23/532 , H01L21/762
CPC分类号： H01L23/49811 , H01L21/76229 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/522 , H01L23/5222 , H01L23/53295 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces.

8. 发明授权

US07855120B2 Methods for forming resistors including multiple layers for integrated circuit devices 有权
标题翻译：用于形成用于集成电路器件的多层电阻器的方法
公开(公告)号：US07855120B2
公开(公告)日：2010-12-21
申请号：US11780026
申请日：2007-07-19
申请人： Je-Min Park , Yoo-Sang Hwang
发明人： Je-Min Park , Yoo-Sang Hwang
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L21/76838 , H01L27/0629
摘要： Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.
摘要翻译：形成集成电路器件的方法可以包括在集成电路衬底上形成绝缘层，在绝缘层上形成第一导电层，在第一导电层上形成第二导电层，使第一导电层位于第二导电层之间导电层和绝缘层。此外，第一导电层可以是第一材料的层，第二导电层可以是第二材料的层，并且第一和第二材料可以不同。可以在第二导电层中形成孔，使得第一导电层的一部分通过该孔露出。在第二导电层中形成孔之后，可以对第一和第二导电层进行图案化，以使第一导电层和第二导电层的围绕通过孔露出的部分的部分被去除，同时保持第一导电层的部分以前暴露在洞里。

9. 发明授权

US07749834B2 Method of fabricating semiconductor devices having buried contact plugs 有权
标题翻译：制造具有埋入式接触塞的半导体器件的方法
公开(公告)号：US07749834B2
公开(公告)日：2010-07-06
申请号：US11364635
申请日：2006-02-27
申请人： Je-Min Park , Yoo-Sang Hwang , Seok-Soon Song
发明人： Je-Min Park , Yoo-Sang Hwang , Seok-Soon Song
IPC分类号： H01L21/8242
CPC分类号： H01L27/10855 , H01L27/10817
摘要： A method includes forming a lower dielectric layer on a semiconductor substrate, forming a bit line landing pad and a storage landing pad that penetrate the lower dielectric layer, covering the lower dielectric layer, the bit line landing pad, and the storage landing pad with an intermediate dielectric layer, forming an upper dielectric layer on the intermediate dielectric layer, partially removing the upper dielectric layer and the intermediate dielectric layer to form a contact opening that exposes the storage landing pad and a portion of the lower dielectric layer, forming a contact spacer on an inner wall of the contact opening, and filling the contact opening with a contact plug, a top surface of the contact plug larger than a surface of the contact plug that is in contact with the storage landing pad, the top surface of the contact plug eccentric in relation to the storage landing pad.
摘要翻译：一种方法包括在半导体衬底上形成下电介质层，形成位线着陆焊盘和穿透下电介质层的存储着陆焊盘，覆盖下电介质层，位线着陆焊盘和存储着陆焊盘中间介电层，在中间介电层上形成上电介质层，部分地去除上电介质层和中间电介质层，以形成暴露存储着陆焊盘和下电介质层的一部分的接触开口，形成接触间隔物在接触开口的内壁上，并用接触塞填充接触开口，接触插塞的顶表面大于接触插塞的与储存着陆垫接触的表面，触头顶表面相对于存储着陆垫插头偏心。

10. 发明申请

US20090087962A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING ALIGNMENT KEY AND SEMICONDUCTOR DEVICE FABRICATED THEREBY 有权
标题翻译：具有对准键的半导体器件的制造方法及其制造的半导体器件
公开(公告)号：US20090087962A1
公开(公告)日：2009-04-02
申请号：US12325694
申请日：2008-12-01
申请人： Min-Hee Cho , Yoo-Sang Hwang , Byung-Hyun Lee
发明人： Min-Hee Cho , Yoo-Sang Hwang , Byung-Hyun Lee
IPC分类号： H01L21/02
CPC分类号： H01L27/10894 , H01L23/544 , H01L27/10814 , H01L28/91 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.
摘要翻译：在制造具有对准键和由此制造的半导体器件的半导体器件的方法中。制造半导体器件的方法包括提供具有划线通道区域和单元区域的半导体衬底。蚀刻阻挡图案和栅极图案分别形成在划线路区域和单元区域上。形成第一层间绝缘层以覆盖蚀刻阻挡图案和栅极图案。分别在划线路区域和单元区域的第一层间绝缘层上形成初步对准键图案和位线图案。形成第二层间绝缘层以覆盖初步对准键图案和位线图案。将第二层间绝缘层和第一层间绝缘层图案化以暴露蚀刻阻挡图案，从而在划线路区域中形成对准键图案，同时在单元区域中形成存储节点接触开口。

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