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1. 发明授权

US06581069B1 Automated activation and deactivation of operational data logging on medical imaging device 失效
标题翻译：自动启动和停用医疗成像设备上的操作数据记录
公开(公告)号：US06581069B1
公开(公告)日：2003-06-17
申请号：US09585218
申请日：2000-06-01
申请人： Naja S. Robinson , Lawrence E. Ploetz , Jie Xue
发明人： Naja S. Robinson , Lawrence E. Ploetz , Jie Xue
IPC分类号： G06F1730
CPC分类号： G06F19/3418 , G06F19/00 , G06F19/324 , G16H15/00 , G16H40/63 , Y10S707/922 , Y10S707/99945
摘要： A method and a system for automatically activating and deactivating a data logging function on a remotely located medical imaging device from a central service facility in response to acquisition of updated service contract information. Customer profiling and service contract data are automatically processed at a central facility to detect that a medical imaging device is now under contract to receive regular scanner utilization reports. The scanner data logging function is then automatically turned on from the central facility. The central facility then monitors the receipt of scanner data log files to ensure that the first data log file has been successfully transmitted from activated medical imaging device, for processing and subsequent utilization report delivery. In the case of an expired service contract, the data logging feature on the medical imaging device is automatically deactivated from the central facility.
摘要翻译：一种方法和系统，用于响应于获取更新的服务契约信息，从中央服务设施自动激活和停用位于远程位置的医疗成像设备上的数据记录功能。客户分析和服务合同数据在中央设施自动处理，以检测医疗成像设备现在正在合同中以接收常规的扫描仪利用率报告。然后，扫描仪数据记录功能将从中央设备自动打开。中央设施然后监视扫描仪数据日志文件的接收，以确保已经从激活的医学成像设备成功传送第一个数据日志文件，以进行处理和随后的使用报告传送。在过期的服务合同的情况下，医疗成像设备上的数据记录功能将从中央设施自动停用。

2. 发明授权

US08689081B2 Techniques for embedded memory self repair 有权
标题翻译：嵌入式内存自我修复技术
公开(公告)号：US08689081B2
公开(公告)日：2014-04-01
申请号：US13304838
申请日：2011-11-28
申请人： Andy Yu , Pierre Chor-Fung Chia , ShiJie Wen , Jie Xue
发明人： Andy Yu , Pierre Chor-Fung Chia , ShiJie Wen , Jie Xue
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.
摘要翻译：提供技术用于对位序列中的错误进行分类和纠正。在存储器控制装置中，请求访问存储在存储器组件的位序列数据库中并与地址相关联的第一位序列。在第一比特序列中检测到错误，并且将与比特序列相关联的地址与存储在内容可寻址存储器组件的地址数据库中的地址进行比较，以确定是否存在匹配。当有匹配时，错误被分类为硬比特错误。当没有匹配时，错误被分类为软比特错误。

3. 发明申请

US20130122658A1 MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING AN EMBEDDED CIRCUIT COMPONENT WITHIN A SUPPORT STRUCTURE OF THE PACKAGE 有权
标题翻译：在包装的支持结构中制造包括嵌入式电路组件的半导体封装
公开(公告)号：US20130122658A1
公开(公告)日：2013-05-16
申请号：US13296707
申请日：2011-11-15
申请人： Jovica Savic , Zhiping Yang , Jie Xue , Li Li
发明人： Jovica Savic , Zhiping Yang , Jie Xue , Li Li
IPC分类号： H01L21/56
CPC分类号： H05K1/183 , H01L23/24 , H01L23/3107 , H01L23/49838 , H01L2224/16225 , H01L2924/0002 , H05K1/115 , H05K1/181 , H05K2201/095 , H05K2201/10492 , H05K2201/10507 , H01L2924/00
摘要： A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.
摘要翻译：提供了一种方法和装置，其中空腔形成在支撑结构中，支撑结构可操作以支撑半导体器件，将电路元件的至少一部分设置在支撑结构中的空腔中，将空腔填充在支撑结构，其具有不导电的填充材料，以至少部分地围绕电路元件与非导电填充材料，并将半导体器件电连接到电路元件。在示例性实施例中，电路元件可操作以基本上阻挡由半导体器件或另一半导体器件输出的直流电流。

4. 发明授权

US08093921B2 Monitoring of interconnect reliability using a programmable device 有权
标题翻译：使用可编程器件监控互连可靠性
公开(公告)号：US08093921B2
公开(公告)日：2012-01-10
申请号：US12370607
申请日：2009-02-13
申请人： Nandakumar Krishnan , Xinli Gu , Li Li , Jie Xue , Jonathan M. Parlan
发明人： Nandakumar Krishnan , Xinli Gu , Li Li , Jie Xue , Jonathan M. Parlan
IPC分类号： G01R31/304 , G01R31/02
CPC分类号： G01R31/026 , G01R31/2894
摘要： In one embodiment, the reliability of the L2 power and/or ground sub-arrays of contacts of a functional integrated circuit device is verified by applying a reference voltage to a selected contact in sub-array and sequentially measuring the voltage at other contacts in the sub-array. If the voltage levels are greater than a threshold voltage level then the functional integrated circuit device is verified as being reliable.
摘要翻译：在一个实施例中，功能集成电路器件的L2电源和/或接地子阵列的可靠性通过将参考电压施加到子阵列中的所选择的触点并且顺序地测量其中的触点的电压来验证子阵列如果电压电平大于阈值电压电平，则功能集成电路器件被验证为可靠的。

5. 发明申请

US20080130241A1 Method and apparatus for supporting a computer chip on a printed circuit board assembly 有权
标题翻译：用于在印刷电路板组件上支撑计算机芯片的方法和装置
公开(公告)号：US20080130241A1
公开(公告)日：2008-06-05
申请号：US11606750
申请日：2006-11-30
申请人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
发明人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
IPC分类号： H05K7/20 , H05K3/34
CPC分类号： H05K1/0271 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H05K1/181 , H05K3/305 , H05K2201/068 , H05K2201/09036 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , Y10T29/49144 , H01L2924/00 , H01L2224/0401
摘要： A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.
摘要翻译：一种印刷电路板组件和组装方法，其中将底部填充物放置在芯片和基板之间以支撑芯片。沟槽形成在印刷电路板的上层中以限制底部填充物的流动，特别是限制底部填充物与相邻部件的接触，使得底部填充物不会干扰印刷电路板组件上的相邻部件。

6. 发明申请

US20120113608A1 METHOD AND APPARATUS FOR SUPPORTING A COMPUTER CHIP ON A PRINTED CIRCUIT BOARD ASSEMBLY 有权
标题翻译：在印刷电路板组件上支持计算机芯片的方法和装置
公开(公告)号：US20120113608A1
公开(公告)日：2012-05-10
申请号：US13292630
申请日：2011-11-09
申请人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
发明人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
IPC分类号： H05K7/06 , H05K3/34
CPC分类号： H05K1/0271 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H05K1/181 , H05K3/305 , H05K2201/068 , H05K2201/09036 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , Y10T29/49144 , H01L2924/00 , H01L2224/0401
摘要： A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.
摘要翻译：一种印刷电路板组件和组装方法，其中将底部填充物放置在芯片和基板之间以支撑芯片。沟槽形成在印刷电路板的上层中以限制底部填充物的流动，特别是限制底部填充物与相邻部件的接触，使得底部填充物不会干扰印刷电路板组件上的相邻部件。

7. 发明申请

US20100207649A1 IN SITU AND REAL TIME MONITORING OF INTERCONNECT RELIABILITY USING A PROGRAMMABLE DEVICE 有权
标题翻译：使用可编程器件进行现场和实时监控互连可靠性
公开(公告)号：US20100207649A1
公开(公告)日：2010-08-19
申请号：US12370607
申请日：2009-02-13
申请人： Nandakumar Krishnan , Xinli Gu , Li Li , Jie Xue , Jonathan M. Parlan
发明人： Nandakumar Krishnan , Xinli Gu , Li Li , Jie Xue , Jonathan M. Parlan
IPC分类号： G01R31/02
CPC分类号： G01R31/026 , G01R31/2894
摘要： In one embodiment, the reliability of the L2 power and/or ground sub-arrays of contacts of a functional integrated circuit device is verified by applying a reference voltage to a selected contact in sub-array and sequentially measuring the voltage at other contacts in the sub-array. If the voltage levels are greater than a threshold voltage level then the functional integrated circuit device is verified as being reliable.
摘要翻译：在一个实施例中，功能集成电路器件的L2电源和/或接地子阵列的可靠性通过将参考电压施加到子阵列中的所选择的触点并且顺序地测量其中的触点的电压来验证子阵列如果电压电平大于阈值电压电平，则功能集成电路器件被验证为可靠的。

8. 发明授权

US08962388B2 Method and apparatus for supporting a computer chip on a printed circuit board assembly 有权
标题翻译：用于在印刷电路板组件上支撑计算机芯片的方法和装置
公开(公告)号：US08962388B2
公开(公告)日：2015-02-24
申请号：US13292630
申请日：2011-11-09
申请人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
发明人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
IPC分类号： H05K7/06 , H05K3/30 , H01L21/56
CPC分类号： H05K1/0271 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H05K1/181 , H05K3/305 , H05K2201/068 , H05K2201/09036 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , Y10T29/49144 , H01L2924/00 , H01L2224/0401
摘要： A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.
摘要翻译：一种印刷电路板组件和组装方法，其中将底部填充物放置在芯片和基板之间以支撑芯片。沟槽形成在印刷电路板的上层中以限制底部填充物的流动，特别是限制底部填充物与相邻部件接触，使得底部填充物不会干扰印刷电路板组件上的相邻部件。

9. 发明申请

US20130139033A1 TECHNIQUES FOR EMBEDDED MEMORY SELF REPAIR 有权
标题翻译：嵌入式记忆自动修复技术
公开(公告)号：US20130139033A1
公开(公告)日：2013-05-30
申请号：US13304838
申请日：2011-11-28
申请人： Andy Yu , Pierre Chor-Fung Chia , ShiJie Wen , Jie Xue
发明人： Andy Yu , Pierre Chor-Fung Chia , ShiJie Wen , Jie Xue
IPC分类号： G06F11/10
CPC分类号： G06F11/1048
摘要： Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.
摘要翻译：提供技术用于对位序列中的错误进行分类和纠正。在存储器控制装置中，请求访问存储在存储器组件的位序列数据库中并与地址相关联的第一位序列。在第一比特序列中检测到错误，并且将与比特序列相关联的地址与存储在内容可寻址存储器组件的地址数据库中的地址进行比较，以确定是否存在匹配。当有匹配时，错误被分类为硬比特错误。当没有匹配时，错误被分类为软比特错误。

10. 发明申请

US20130015557A1 SEMICONDUCTOR PACKAGE INCLUDING AN EXTERNAL CIRCUIT ELEMENT 审中-公开
标题翻译：包含外部电路元件的半导体封装
公开(公告)号：US20130015557A1
公开(公告)日：2013-01-17
申请号：US13181899
申请日：2011-07-13
申请人： Zhiping Yang , Jie Xue , Jovica Savic , Li Li
发明人： Zhiping Yang , Jie Xue , Jovica Savic , Li Li
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L23/49822 , H01L23/50 , H01L24/05 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/12042 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1304 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K1/0243 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： Circuit elements such as DC blocking capacitors used in communication such as a serial communication link between two or more electrical components are disposed in pre-existing openings in a support structure that supports at least one of the two electrical components. The openings may be plated and used for signal transmission from the one electrical component to a printed circuit board (PCB) supporting the substrate. The DC blocking capacitors may be oriented substantially vertically, and a non-conducting material may be disposed in each opening in the substrate such that the non-conducting material at least partially surrounds and fixes the orientation of the DC blocking capacitor disposed in the opening.
摘要翻译：在诸如两个或更多个电气部件之间的串行通信链路的通信中使用的诸如隔直流电容器之类的电路元件被布置在支撑结构中的预先存在的开口中，该支撑结构支撑两个电气部件中的至少一个。开口可以被电镀并用于从一个电气部件到支撑衬底的印刷电路板（PCB）的信号传输。隔直电容器可以基本垂直地定向，并且非导电材料可以设置在基板中的每个开口中，使得非导电材料至少部分地围绕并固定设置在开口中的隔直流电容器的取向。

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