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1. 发明申请

US20120074557A1 Integrated Circuit Package Lid Configured For Package Coplanarity 有权
标题翻译：集成电路封装盖配置为封装共面性
公开(公告)号：US20120074557A1
公开(公告)日：2012-03-29
申请号：US12891088
申请日：2010-09-27
申请人： Mudasir Ahmad , Mohan R. Nagar , Weidong Xie
发明人： Mudasir Ahmad , Mohan R. Nagar , Weidong Xie
IPC分类号： H01L23/48 , H01L21/02
CPC分类号： H01L23/3675 , H01L23/49816 , H01L2924/15311 , Y10T428/24066 , Y10T428/24198
摘要： An integrated circuit package apparatus comprises a packaging substrate, an integrated circuit coupled to an upper side of the packaging substrate, an array of contacts coupled to an underside of the packaging substrate for electrically coupling the integrated circuit to a circuit board, and a lid coupled to the upper side of the packaging substrate. In one form, the lid includes a central portion lying on a first plane, corner areas lying on a second plane, and arcuate wall portions disposed between and interconnecting the corner areas and the central portion. Other forms of the lid are provided.
摘要翻译：集成电路封装装置包括封装基板，耦合到封装基板的上侧的集成电路，耦合到封装基板的下侧的触点阵列，用于将集成电路电耦合到电路板，以及盖耦合到包装基板的上侧。在一种形式中，盖包括位于第一平面上的中心部分，位于第二平面上的拐角区域以及设置在拐角区域和中心部分之间并将其相互连接的弓形壁部分。提供其他形式的盖子。

2. 发明授权

US06605954B1 Reducing probe card substrate warpage 有权
标题翻译：减少探针卡基板翘曲
公开(公告)号：US06605954B1
公开(公告)日：2003-08-12
申请号：US10055812
申请日：2002-01-23
申请人： Mohan R. Nagar
发明人： Mohan R. Nagar
IPC分类号： G01R3102
CPC分类号： G01R1/07307 , G01R3/00
摘要： An electrically non conducting material disposed within one or more of the voids of a probe card between a substrate thereof and a tester interface to reinforce the substrate against flexing, bending, and warpage.
摘要翻译：布置在探针卡的一个或多个空隙之间的非导电材料，在其基底和测试器界面之间，以加强基底以防挠曲，弯曲和翘曲。

3. 发明申请

US20130284796A1 SYSTEM IN PACKAGE MODULE ASSEMBLY 审中-公开
标题翻译：封装模块组件系统
公开(公告)号：US20130284796A1
公开(公告)日：2013-10-31
申请号：US13455908
申请日：2012-04-25
申请人： Mohan R. Nagar , Mudasir Ahmad
发明人： Mohan R. Nagar , Mudasir Ahmad
IPC分类号： B23K31/02 , B23K37/00
CPC分类号： B23K1/0016 , H01L23/16 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0655 , H01L25/16 , H01L2224/13111 , H01L2224/13147 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81001 , H01L2224/81136 , H01L2224/81191 , H01L2224/81203 , H01L2224/8121 , H01L2224/81815 , H01L2224/83001 , H01L2224/83855 , H01L2224/83862 , H01L2224/92125 , H01L2924/14 , H01L2924/1434 , H01L2924/15311 , H01L2924/19105 , H01L2924/3511 , H01L2924/00012 , H01L2924/00
摘要： In one implementation, a system in package assembly process includes attaching a cladding to a substrate to keep the substrate flat while components are soldered onto the substrate. The cladding may include a supporting member and a clamping member, and the substrate may be received between the clamping member and the supporting member. The clamping member may have a plurality of openings formed therein, and the components may be positioned on the substrate within at least one of the plurality of openings. A predetermined pressure may be applied to the clamping member and/or supporting to keep the substrate flat.
摘要翻译：在一个实施方案中，包装组装过程中的系统包括将包层附接到基底以在保持基底平坦的同时将部件焊接到基底上。包层可以包括支撑构件和夹紧构件，并且衬底可以被容纳在夹紧构件和支撑构件之间。夹紧构件可以具有形成在其中的多个开口，并且部件可以位于多个开口中的至少一个开口中的基板上。可以将预定的压力施加到夹持构件和/或支撑件以使基板保持平坦。

4. 发明申请

US20080130241A1 Method and apparatus for supporting a computer chip on a printed circuit board assembly 有权
标题翻译：用于在印刷电路板组件上支撑计算机芯片的方法和装置
公开(公告)号：US20080130241A1
公开(公告)日：2008-06-05
申请号：US11606750
申请日：2006-11-30
申请人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
发明人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
IPC分类号： H05K7/20 , H05K3/34
CPC分类号： H05K1/0271 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H05K1/181 , H05K3/305 , H05K2201/068 , H05K2201/09036 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , Y10T29/49144 , H01L2924/00 , H01L2224/0401
摘要： A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.
摘要翻译：一种印刷电路板组件和组装方法，其中将底部填充物放置在芯片和基板之间以支撑芯片。沟槽形成在印刷电路板的上层中以限制底部填充物的流动，特别是限制底部填充物与相邻部件的接触，使得底部填充物不会干扰印刷电路板组件上的相邻部件。

5. 发明授权

US07352062B2 Integrated circuit package design 有权
标题翻译：集成电路封装设计
公开(公告)号：US07352062B2
公开(公告)日：2008-04-01
申请号：US10979491
申请日：2004-11-02
申请人： Mukul A. Joshi , Mohan R. Nagar , Sarathy Rajagopalan
发明人： Mukul A. Joshi , Mohan R. Nagar , Sarathy Rajagopalan
IPC分类号： H01L23/10 , H01L23/34
CPC分类号： H01L23/36 , H01L23/42 , H01L23/4334 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2924/16152 , H01L2924/3025 , H01L2224/0401
摘要： A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.
摘要翻译：一种封装集成电路，包括具有用于接收集成电路的电触点的封装基板。集成电路电连接到封装衬底的电触头。加强件安装到封装基板上，其中加强件具有非正交切口，集成电路设置在其中。切出的边缘设置在与集成电路的侧面不同于集成电路的角落的距离以上。

6. 发明授权

US08962388B2 Method and apparatus for supporting a computer chip on a printed circuit board assembly 有权
标题翻译：用于在印刷电路板组件上支撑计算机芯片的方法和装置
公开(公告)号：US08962388B2
公开(公告)日：2015-02-24
申请号：US13292630
申请日：2011-11-09
申请人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
发明人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
IPC分类号： H05K7/06 , H05K3/30 , H01L21/56
CPC分类号： H05K1/0271 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H05K1/181 , H05K3/305 , H05K2201/068 , H05K2201/09036 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , Y10T29/49144 , H01L2924/00 , H01L2224/0401
摘要： A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.
摘要翻译：一种印刷电路板组件和组装方法，其中将底部填充物放置在芯片和基板之间以支撑芯片。沟槽形成在印刷电路板的上层中以限制底部填充物的流动，特别是限制底部填充物与相邻部件接触，使得底部填充物不会干扰印刷电路板组件上的相邻部件。

7. 发明授权

US06717423B1 Substrate impedance measurement 有权
标题翻译：基板阻抗测量
公开(公告)号：US06717423B1
公开(公告)日：2004-04-06
申请号：US10267814
申请日：2002-10-09
申请人： Aritharan Thurairajaratnam , Mohan R. Nagar
发明人： Aritharan Thurairajaratnam , Mohan R. Nagar
IPC分类号： G01R3102
CPC分类号： G01R31/2805 , G01R1/07314 , G01R27/04
摘要： A probe structure with a connector connecting the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. A back side layer is connected to the connector. A probe side layer with contacts is sandwiched with the back side layer in a layered substrate. The probe side layer has a centrally disposed signal contact and surrounding ground contacts. A conductive layer is disposed between the back side layer and the probe side layer. The conductive layer is connected to the ground conductor of the connector and to the ground contacts of the probe side layer contacts. A via extends from the back side layer to the probe side layer. The via is connected to the signal conductor of the connector, and is also connected to the centrally disposed signal contact of the probe side layer contacts. The via does not make connection with the conductive layer. A first of pins is connected to the signal contact, for making a connection with a structure to be tested on the package substrate. Others of the pins are connected to the ground contacts, for making connections with structures on the package substrate that surround the structure to be tested.
摘要翻译：探针结构，其具有将探针结构连接到时域反射测试仪的连接器，其中连接器具有信号导体和接地导体。背面层连接到连接器。具有触点的探针侧层与层叠基板中的背面层夹持。探头侧层具有中心设置的信号触点和周围的接地触点。导电层设置在背侧层和探针侧层之间。导电层连接到连接器的接地导体和探头侧层触点的接地触头。通孔从背侧层延伸到探针侧层。通孔连接到连接器的信号导体，并且还连接到探头侧层触点的中心布置的信号触点。通孔不与导电层连接。第一个引脚连接到信号触点，用于与封装衬底上要测试的结构进行连接。其他引脚连接到接地触点，用于与围绕待测结构的封装基板上的结构进行连接。

8. 发明授权

US08952523B2 Integrated circuit package lid configured for package coplanarity 有权
标题翻译：集成电路封装盖配置为封装共面性
公开(公告)号：US08952523B2
公开(公告)日：2015-02-10
申请号：US12891088
申请日：2010-09-27
申请人： Mudasir Ahmad , Mohan R. Nagar , Weidong Xie
发明人： Mudasir Ahmad , Mohan R. Nagar , Weidong Xie
IPC分类号： H01L23/12 , H01L23/367 , H01L23/498
CPC分类号： H01L23/3675 , H01L23/49816 , H01L2924/15311 , Y10T428/24066 , Y10T428/24198
摘要： An integrated circuit package apparatus includes a packaging substrate, an integrated circuit coupled to an upper side of the packaging substrate, an array of contacts coupled to an underside of the packaging substrate for electrically coupling the integrated circuit to a circuit board, and a lid coupled to the upper side of the packaging substrate. In one form, the lid includes a central portion lying on a first plane, corner areas lying on a second plane, and arcuate wall portions disposed between and interconnecting the corner areas and the central portion. Other forms of the lid are provided.
摘要翻译：集成电路封装装置包括封装衬底，耦合到封装衬底的上侧的集成电路，耦合到封装衬底的下侧的触点阵列，用于将集成电路电耦合到电路板，以及将耦合到包装基板的上侧。在一种形式中，盖包括位于第一平面上的中心部分，位于第二平面上的拐角区域，以及设置在拐角区域和中心部分之间并将其相互连接的弓形壁部分。提供其他形式的盖子。

9. 发明申请

US20120113608A1 METHOD AND APPARATUS FOR SUPPORTING A COMPUTER CHIP ON A PRINTED CIRCUIT BOARD ASSEMBLY 有权
标题翻译：在印刷电路板组件上支持计算机芯片的方法和装置
公开(公告)号：US20120113608A1
公开(公告)日：2012-05-10
申请号：US13292630
申请日：2011-11-09
申请人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
发明人： Mohan R. Nagar , Kuo-Chuan Liu , Mudasir Ahmad , Bangalore J. Shanker , Jie Xue
IPC分类号： H05K7/06 , H05K3/34
CPC分类号： H05K1/0271 , H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H05K1/181 , H05K3/305 , H05K2201/068 , H05K2201/09036 , H05K2201/10674 , H05K2201/10977 , Y02P70/613 , Y10T29/49144 , H01L2924/00 , H01L2224/0401
摘要： A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.
摘要翻译：一种印刷电路板组件和组装方法，其中将底部填充物放置在芯片和基板之间以支撑芯片。沟槽形成在印刷电路板的上层中以限制底部填充物的流动，特别是限制底部填充物与相邻部件的接触，使得底部填充物不会干扰印刷电路板组件上的相邻部件。

10. 发明授权

US06891392B2 Substrate impedance measurement 有权
标题翻译：基板阻抗测量
公开(公告)号：US06891392B2
公开(公告)日：2005-05-10
申请号：US10371386
申请日：2003-02-21
申请人： Mohan R. Nagar , Aritharan Thurairajaratnam
发明人： Mohan R. Nagar , Aritharan Thurairajaratnam
IPC分类号： G01R1/073 , G01R31/26 , H01H31/02
CPC分类号： G01R1/07314
摘要： A probe structure for testing impedance of a package substrate using time domain reflectometry. A connector electrically connects the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. An electrically conductive cantilever signal pin is electrically connected to the signal conductor. The electrically conductive cantilever signal pin has a tip for making an electrical connection with an electrically conductive structure to be tested on the package substrate. The electrically conductive cantilever signal pin is electrically isolated by and sheathed within a ground shield that is electrically connected to at least one of the ground conductor and electrically conductive cantilever ground pins. The electrically conductive cantilever ground pins are electrically connected to the ground conductor. The electrically conductive cantilever ground pins also have tips, for making electrical connections with electrically conductive structures on the package substrate that surround the electrically conductive structure to be tested on the package substrate.
摘要翻译：用于使用时域反射测试来测试封装衬底的阻抗的探针结构。连接器将探针结构电连接到时域反射测试仪，其中连接器具有信号导体和接地导体。导电悬臂信号引脚电连接到信号导体。导电悬臂信号销具有用于与要在导体上进行测试的导电结构进行电连接的尖端。导电悬臂信号引脚在接地屏蔽内电隔离并被电连接到接地导体和导电悬臂接地引脚中的至少一个。导电悬臂接地引脚电连接到接地导体。导电悬臂接地引脚还具有尖端，用于与围绕要在封装衬底上测试的导电结构的封装衬底上的导电结构进行电连接。

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