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1. 发明申请

US20060157773A1 Non-volatile electrically alterable memory cell for storing multiple data and manufacturing thereof 审中-公开
标题翻译：用于存储多个数据及其制造的非易失性电可变存储单元
公开(公告)号：US20060157773A1
公开(公告)日：2006-07-20
申请号：US11036911
申请日：2005-01-14
申请人： Andy Yu , Ying Go
发明人： Andy Yu , Ying Go
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7887 , H01L29/7923
摘要： A memory cell that includes two control gates disposed laterally between two floating gates where each floating gate is capable of holding data. The memory cell is formed by placing a first polysilicon on a substrate of semiconductor material, on which a well is placed. The control gates are preferably formed by a Damascene process, in which a first polysilicon is removed after forming two floating gates, and a second polysilicon is placed between these two floating gates. An anisotropic etching is later done on the second polysilicon to form two control gates.
摘要翻译：一种存储单元，包括两个控制门，横向设置在两个浮动栅极之间，每个浮动栅极能够保存数据。存储单元通过将第一多晶硅放置在其上放置有阱的半导体材料的衬底上而形成。控制栅极优选地通过镶嵌工艺形成，其中在形成两个浮置栅极之后去除第一多晶硅，并且在这两个浮置栅极之间放置第二多晶硅。稍后在第二多晶硅上进行各向异性蚀刻以形成两个控制栅极。

2. 发明申请

US20060081910A1 Non-volatile electrically alterable memory cell for storing multiple data and an array thereof 审中-公开
标题翻译：用于存储多个数据的非易失性电可变存储器单元及其阵列
公开(公告)号：US20060081910A1
公开(公告)日：2006-04-20
申请号：US11292922
申请日：2005-12-02
申请人： Andy Yu , Ying Go
发明人： Andy Yu , Ying Go
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114 , H01L29/7887
摘要： A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.
摘要翻译：一种存储单元，包括一个横向设置在两个浮动栅极之间的控制栅极，每个浮动栅极能够保存数据。存储器单元中的每个浮置栅极可以通过将电压组合施加到扩散区域，控制栅极和阱来被擦除和编程。多个存储器单元产生存储器串，并且存储器阵列由以行和列排列的多个存储器串形成。

3. 发明授权

US08770992B2 Leakage current detection interrupter plug having detachable connect terminals 失效
标题翻译：泄漏电流检测断路器插头具有可拆卸的连接端子
公开(公告)号：US08770992B2
公开(公告)日：2014-07-08
申请号：US13559100
申请日：2012-07-26
申请人： Andy Yu , Ji Han , Chepur P. Rao , Victor V. Aromin
发明人： Andy Yu , Ji Han , Chepur P. Rao , Victor V. Aromin
IPC分类号： H01R13/514
CPC分类号： H01R11/11 , H01R13/02 , H01R13/24 , H01R13/41 , H01R13/6658 , H01R24/00 , H01R24/28
摘要： An electric plug includes an end block and a power cord. The end block includes a plurality of first connectors and the power cord includes a plurality of second connectors which correspond to the first connectors and detachably connected thereto. The first connectors and second connectors are electrically conductive. One or more first connectors are connected to the second connectors by press-fitting and are retained therewith by friction. Alternatively, the first connectors may be a terminal screw assembly and the second connectors are wires of the power cord.
摘要翻译：电插头包括端块和电源线。端块包括多个第一连接器，并且电源线包括对应于第一连接器并可拆卸地连接到其上的多个第二连接器。第一连接器和第二连接器是导电的。一个或多个第一连接器通过压配合连接到第二连接器，并通过摩擦保持在其上。或者，第一连接器可以是端子螺钉组件，第二连接器是电源线的导线。

4. 发明授权

US08689081B2 Techniques for embedded memory self repair 有权
标题翻译：嵌入式内存自我修复技术
公开(公告)号：US08689081B2
公开(公告)日：2014-04-01
申请号：US13304838
申请日：2011-11-28
申请人： Andy Yu , Pierre Chor-Fung Chia , ShiJie Wen , Jie Xue
发明人： Andy Yu , Pierre Chor-Fung Chia , ShiJie Wen , Jie Xue
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.
摘要翻译：提供技术用于对位序列中的错误进行分类和纠正。在存储器控制装置中，请求访问存储在存储器组件的位序列数据库中并与地址相关联的第一位序列。在第一比特序列中检测到错误，并且将与比特序列相关联的地址与存储在内容可寻址存储器组件的地址数据库中的地址进行比较，以确定是否存在匹配。当有匹配时，错误被分类为硬比特错误。当没有匹配时，错误被分类为软比特错误。

5. 发明授权

US07276759B1 Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling 失效
标题翻译：具有控制和浮动栅极和侧壁耦合的非易失性电气可变半导体存储器
公开(公告)号：US07276759B1
公开(公告)日：2007-10-02
申请号：US10798138
申请日：2004-03-11
申请人： Andy Yu , Ying W. Go
发明人： Andy Yu , Ying W. Go
IPC分类号： H01L29/788
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11519
摘要： In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.
摘要翻译：在存储单元阵列中，每个存储单元包括一个横向设置在浮动栅极附近的控制栅极。每个存储器列中的存储单元设置在单个阱内。控制栅极和浮置栅极设置在两个扩散区域之间。可以通过将电压组合施加到扩散区域，控制栅极和阱来擦除和编程每个存储器单元。

6. 发明授权

US07172528B2 Transfer case with overdrive/underdrive shifting 有权
标题翻译：转速超速/欠驱动换档
公开(公告)号：US07172528B2
公开(公告)日：2007-02-06
申请号：US10773108
申请日：2004-02-05
申请人： Andy Yu , Fredric H. Tubbs , Thomas J. Foster
发明人： Andy Yu , Fredric H. Tubbs , Thomas J. Foster
IPC分类号： F16H3/44
CPC分类号： B60K17/3467
摘要： A transfer case for a vehicle that includes a planetary gear assembly, a clutch pack assembly, and a band and drum assembly that provide an overdrive or underdrive and direct drive in combination with a vehicle transmission. In one embodiment, an input shaft drives an outer ring gear of the planetary gear assembly and is coupled to one set of discs of the clutch assembly. A carrier of the planetary gear assembly is coupled to a rear output shaft, where the carrier supports a plurality of pinion gears. A sun gear of the planetary gear assembly is coupled to another set of discs of the clutch assembly that are coupled to the drum. When the clutch assembly is engaged, the ring gear is coupled to the sun gear for direct drive and when the band is engaged, the pinion gears and the ring gear provide underdrive.
摘要翻译：一种用于车辆的分动箱，包括行星齿轮组件，离合器组件以及与车辆变速器组合提供过驱动或欠驱动和直接驱动的带和鼓组件。在一个实施例中，输入轴驱动行星齿轮组件的外齿圈并且联接到离合器组件的一组盘。行星齿轮组件的载体联接到后输出轴，其中载体支撑多个小齿轮。行星齿轮组件的太阳齿轮联接到耦合到滚筒的离合器组件的另一组盘。当离合器组件接合时，齿圈联接到太阳齿轮用于直接驱动，并且当带接合时，小齿轮和齿圈提供欠驱动。

7. 发明申请

US20130330939A1 LEAKAGE CURRENT DETECTION INTERRUPTER PLUG HAVING DETACHABLE CONNECT TERMINALS 失效
标题翻译：具有可拆卸连接端子的漏电流检测中断插头
公开(公告)号：US20130330939A1
公开(公告)日：2013-12-12
申请号：US13559100
申请日：2012-07-26
申请人： Andy Yu , Ji Han , Chepur P. Rao , Victor V. Aromin
发明人： Andy Yu , Ji Han , Chepur P. Rao , Victor V. Aromin
IPC分类号： H01R24/28 , H01R12/75
CPC分类号： H01R11/11 , H01R13/02 , H01R13/24 , H01R13/41 , H01R13/6658 , H01R24/00 , H01R24/28
摘要： An electric plug includes an end block and a power cord. The end block includes a plurality of first connectors and the power cord includes a plurality of second connectors which correspond to the first connectors and detachably connected thereto. The first connectors and second connectors are electrically conductive. One or more first connectors are connected to the second connectors by press-fitting and are retained therewith by friction. Alternatively, the first connectors may be a terminal screw assembly and the second connectors are wires of the power cord.
摘要翻译：电插头包括端块和电源线。端块包括多个第一连接器，并且电源线包括对应于第一连接器并可拆卸地连接到其上的多个第二连接器。第一连接器和第二连接器是导电的。一个或多个第一连接器通过压配合连接到第二连接器，并通过摩擦保持在其上。或者，第一连接器可以是端子螺钉组件，第二连接器是电源线的导线。

8. 发明授权

US07834388B2 Memory array of non-volatile electrically alterable memory cells for storing multiple data 有权
标题翻译：用于存储多个数据的非易失性电可变存储器单元的存储器阵列
公开(公告)号：US07834388B2
公开(公告)日：2010-11-16
申请号：US11348556
申请日：2006-02-06
申请人： Andy Yu , Ying W. Go
发明人： Andy Yu , Ying W. Go
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/11521 , G11C16/0408 , H01L21/28273 , H01L27/115 , H01L27/11524 , H01L29/7887
摘要： A memory cell that includes a control gate disposed laterally between two floating gates where each floating gate is capable of holding data. Each floating gate in a memory cell may be erased and programmed by applying a combination of voltages to diffusion regions, the control gate, and a well. A plurality of memory cells creates a memory string, and a memory array is formed from a plurality of memory strings arranged in rows and columns.
摘要翻译：一种存储单元，包括一个横向设置在两个浮动栅极之间的控制栅极，每个浮动栅极能够保存数据。存储器单元中的每个浮置栅极可以通过将电压组合施加到扩散区域，控制栅极和阱来被擦除和编程。多个存储器单元产生存储器串，并且存储器阵列由以行和列排列的多个存储器串形成。

9. 发明授权

US07449744B1 Non-volatile electrically alterable memory cell and use thereof in multi-function memory array 有权
标题翻译：非易失性电可变存储器单元及其在多功能存储器阵列中的应用
公开(公告)号：US07449744B1
公开(公告)日：2008-11-11
申请号：US10910198
申请日：2004-08-03
申请人： Andy Yu , Ying W. Go
发明人： Andy Yu , Ying W. Go
IPC分类号： H01L23/62 , H01L29/93
CPC分类号： H01L29/66825 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7881
摘要： A multi-function memory array that includes a DRAM distributed in several DRAM sectors, a Flash EEPROM distributed in several Flash EEPROM sectors, a data bus interconnecting the DRAM sectors and the Flash EEPROM sectors, and a plurality of memory access control circuitries. Each DRAM sector and Flash EEPROM sector can be accessed independently and data can be transferred between a DRAM sector and a Flash EEPROM sector. External data can also be written into either DRAM or Flash EEPROM. Flash EEPROM in one sector is distributed in rows and columns, and cells in each column are separated from the cells in an adjacent column by deep trench isolation regions.
摘要翻译：包括分布在几个DRAM扇区中的DRAM，分布在几个闪存EEPROM扇区中的闪存EEPROM，互连DRAM扇区和闪存EEPROM扇区的数据总线以及多个存储器访问控制电路的多功能存储器阵列。可以独立地访问每个DRAM扇区和闪存EEPROM扇区，并且可以在DRAM扇区和闪存EEPROM扇区之间传输数据。外部数据也可以写入DRAM或闪存EEPROM。一个扇区中的闪存EEPROM分布在行和列中，每个列中的单元格通过深沟槽隔离区域与相邻列中的单元格分离。

10. 发明申请

US20070297246A1 NON-VOLATILE ELECTRICALLY ALTERABLE SEMICONDUCTOR MEMORY WITH CONTROL AND FLOATING GATES AND SIDE-WALL COUPLING 审中-公开
标题翻译：具有控制和浮动门和侧壁耦合的非易失性电气可更换半导体存储器
公开(公告)号：US20070297246A1
公开(公告)日：2007-12-27
申请号：US11851913
申请日：2007-09-07
申请人： Andy Yu , Ying Go
发明人： Andy Yu , Ying Go
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11519
摘要： In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.
摘要翻译：在存储单元阵列中，每个存储单元包括一个横向设置在浮动栅极附近的控制栅极。每个存储器列中的存储单元设置在单个阱内。控制栅极和浮置栅极设置在两个扩散区域之间。可以通过将电压组合施加到扩散区域，控制栅极和阱来擦除和编程每个存储器单元。

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