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1. 发明授权

US06691288B1 Method to debug IKOS method 失效
标题翻译： ikos模型的调试方法
公开(公告)号：US06691288B1
公开(公告)日：2004-02-10
申请号：US10034535
申请日：2001-12-27
申请人： Nader Fakhry , Viswanathan Lakshmanan , Jayendra P. Gagvani
发明人： Nader Fakhry , Viswanathan Lakshmanan , Jayendra P. Gagvani
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method of debugging an IKOS model. The method includes mapping information contained in either a .pin or .lde file or both into corresponding files which are more user-friendly, readable and editable. Preferably, a .v file which is readable to create a schematic view of the cell is also created and the schematic view can be viewed and analyzed. Then, the one or more user-friendly files which have been created can be read and edited, and the .pin and/or the .lde file is re-created. Then, a tool is used to analyze the .pin and .lde files again and determine whether there is a functional or timing failure.
摘要翻译：一种调试IKOS模型的方法。该方法包括将.pin或.lde文件中包含的信息映射到更加用户友好，可读和可编辑的相应文件中。优选地，还创建了可读取以创建单元的示意图的.v文件，并且可以查看和分析示意图。然后，可以读取和编辑已创建的一个或多个用户友好的文件，并重新创建.pin和/或.lde文件。然后，使用工具再次分析.pin和.lde文件，并确定是否存在功能或时序故障。

2. 发明授权

US06668359B1 Verilog to vital translator 失效
标题翻译：重要翻译Verilog
公开(公告)号：US06668359B1
公开(公告)日：2003-12-23
申请号：US10003823
申请日：2001-10-31
申请人： Nader Fakhry , Viswanathan Lakshmanan
发明人： Nader Fakhry , Viswanathan Lakshmanan
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method of translating a register transfer level code model includes receiving as inputs a user defined primitives map file, a truth table map file, a gate primitives map file, a register transfer level description file of a library cell, a standard delay format file, and a pin order information file for the register transfer level code model; creating data structures for a VITAL model; parsing at least one of the user defined primitives map file, the truth table map file, the gate primitives map file, the register transfer level description file, and the standard delay format file to generate an equivalent VITAL model in the data structures created for the VITAL model wherein the VITAL model is functionally equivalent to the register transfer level code model; and generating as output a VITAL model file from the data structures created for the VITAL model.
摘要翻译：一种翻译寄存器传送级代码模型的方法包括：接收用户定义的基元映射文件，真值表映射文件，门基元映射文件，库单元的寄存器传输级别描述文件，标准延迟格式文件，以及用于寄存器传送级代码模型的引脚顺序信息文件; 为VITAL模型创建数据结构; 解析用户定义的基元映射文件，真值表映射文件，门基元映射文件，寄存器传输级别描述文件和标准延迟格式文件中的至少一个，以在针对所创建的数据结构中生成等价的VITAL模型 VITAL模型，其中VITAL模型在功能上等同于寄存器传送级代码模型; 并从为VITAL模型创建的数据结构中生成VITAL模型文件作为输出。

3. 发明授权

US07260803B2 Incremental dummy metal insertions 有权
标题翻译：增量的虚拟金属插入
公开(公告)号：US07260803B2
公开(公告)日：2007-08-21
申请号：US10683369
申请日：2003-10-10
申请人： Viswanathan Lakshmanan , Richard Blinne , Vikram Shrowty , Lena Montecillo
发明人： Viswanathan Lakshmanan , Richard Blinne , Vikram Shrowty , Lena Montecillo
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method and system for performing dummy metal insertion in design data for an integrated circuit is disclosed, wherein the design data includes dummy metal objects inserted by a dummy fill tool. After a portion of the design data is changed, a check is performed to determine whether any dummy metal objects intersect with any other objects in the design data. If so, the intersecting dummy metal objects are deleted from the design data, thereby avoiding having to rerun the dummy fill tool.
摘要翻译：公开了一种用于在集成电路的设计数据中执行虚拟金属插入的方法和系统，其中设计数据包括由虚拟填充工具插入的虚拟金属物体。在设计数据的一部分改变之后，执行检查以确定任何虚拟金属物体是否与设计数据中的任何其他对象相交。如果是这样，则从设计数据中删除相交的虚拟金属物体，从而避免重新运行虚拟填充工具。

4. 发明授权

US07149989B2 Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design 有权
公开(公告)号：US07149989B2
公开(公告)日：2006-12-12
申请号：US10947498
申请日：2004-09-22
申请人： Viswanathan Lakshmanan , Alan Holesovsky , Lisa M. Miller , Jonathan P. Kuppinger
发明人： Viswanathan Lakshmanan , Alan Holesovsky , Lisa M. Miller , Jonathan P. Kuppinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits in the integrated circuit design and power distribution and input/output cell placement in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific rule deck.

5. 发明申请

US20060136855A1 Method of implementing an engineering change order in an integrated circuit design by windows 有权
标题翻译：通过Windows实现集成电路设计中的工程变更顺序的方法
公开(公告)号：US20060136855A1
公开(公告)日：2006-06-22
申请号：US11015123
申请日：2004-12-17
申请人： Jason Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel Prevedel , Richard Blinne , Jonathan Kuppinger
发明人： Jason Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel Prevedel , Richard Blinne , Jonathan Kuppinger
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/04
摘要： A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.
摘要翻译：一种实现工程变更订单的方法包括以下步骤：（a）接收作为输入的集成电路设计; （b）作为输入接收集成电路设计的工程变更订单; （c）在集成电路设计中创建至少一个窗口，其包围由工程改变顺序引入的集成电路设计的变化，其中窗口由限定小于集成电路的整个区域的区域的坐标界定设计; （d）执行集成电路设计的路由，该路由排除不包括窗口的任何网络的路由; （e）将由窗口坐标限定的集成电路设计的副本中的区域替换为增量路由的结果以生成修订的集成电路设计; 和（f）产生经修订的集成电路设计的输出。

6. 发明授权

US07051318B1 Web based OLA memory generator 有权
标题翻译：基于Web的OLA内存生成器
公开(公告)号：US07051318B1
公开(公告)日：2006-05-23
申请号：US09973153
申请日：2001-10-09
申请人： Viswanathan Lakshmanan , Cristian T. Crisan , Balaji Ekambaram , Eugene V. Anikin
发明人： Viswanathan Lakshmanan , Cristian T. Crisan , Balaji Ekambaram , Eugene V. Anikin
IPC分类号： G06F9/44
CPC分类号： G06F8/30 , G06F8/41
摘要： A system for generating an Open Library Architecture Delay and Power Calculation Module. The system includes a user interface for generating and submitting requests that specify configurations and types of memories for which Open Library Architecture Delay and Power Calculation Modules are needed. A server is configured to received the requests and produce Open Library Architecture Delay and Power Calculation Modules in response thereto.
摘要翻译：一种用于生成开放库体系结构延迟和功率计算模块的系统。该系统包括用于生成和提交请求的用户界面，该请求指定需要开放库体系结构延迟和功率计算模块的存储器的配置和类型。服务器被配置为接收请求并产生响应于此的开放库架构延迟和功率计算模块。

7. 发明申请

US20070157140A1 Method and computer program product for trimming the analysis of physical layout versus schematic design comparison 失效
标题翻译：用于修整物理布局分析与原理图设计比较的方法和计算机程序产品
公开(公告)号：US20070157140A1
公开(公告)日：2007-07-05
申请号：US11321260
申请日：2005-12-29
申请人： Alan Holesovsky , Viswanathan Lakshmanan , Brent Acott
发明人： Alan Holesovsky , Viswanathan Lakshmanan , Brent Acott
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method, a computer program product, and an apparatus for performing a trimmed verification analysis comprising selecting layers of interest for a trimmed analysis, eliminating layer definitions for unselected layers to create a trimmed rundeck, and performing a layout versus schematic verification comparison to generate a trimmed error report for the selected layers of interest.
摘要翻译：一种用于执行修整的验证分析的方法，计算机程序产品和装置，包括选择用于修剪分析的感兴趣的层，消除未选择的层的层定义以创建修整的破碎，以及执行布局与示意图验证比较以产生修剪所选图层的错误报告。

8. 发明授权

US07107559B2 Method of partitioning an integrated circuit design for physical design verification 有权
标题翻译：分离用于物理设计验证的集成电路设计的方法
公开(公告)号：US07107559B2
公开(公告)日：2006-09-12
申请号：US10697357
申请日：2003-10-29
申请人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
发明人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A method of partitioning an integrated circuit design for physical design verification includes steps of receiving as input a representation of an integrated circuit design having a number of physical design layers and a composite run deck specifying rule checks to be performed on the integrated circuit design. The composite run deck is partitioned into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum. The representation of the integrated circuit design is parsed to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks. The filtered data deck is generated as output for each of the partitioned run decks.
摘要翻译：对用于物理设计验证的集成电路设计进行分区的方法包括以下步骤：接收作为输入的具有多个物理设计层的集成电路设计的表示，以及指定要对集成电路设计执行的规则检查的复合运行层。复合运行甲板被划分为分区运行甲板，使得每个分区运行甲板引用的物理设计层的数量是最小的。解析集成电路设计的表示仅将每个分区运行平台所需的物理设计层过滤到每个分区运行卡的过滤数据卡。过滤的数据记录卡是为每个分区运行记录卡的输出生成的。

9. 发明授权

US07007248B2 Method and apparatus for implementing engineering change orders 有权
标题翻译：实施工程变更单的方法和装置
公开(公告)号：US07007248B2
公开(公告)日：2006-02-28
申请号：US10439373
申请日：2003-05-15
申请人： Richard Blinne , Viswanathan Lakshmanan , Venugopalan Pranesan
发明人： Richard Blinne , Viswanathan Lakshmanan , Venugopalan Pranesan
IPC分类号： G06F17/50 , G06F19/00 , G06F7/00 , G06F17/30
CPC分类号： G06F17/5045 , Y10S707/99931 , Y10S707/99945
摘要： A tool and method for implementing engineering change orders. The tool and method provides that a change file is checked, equivalent engineering change orders are computed and applied to an active cell. The engineering change orders are registered with a pre-determined tool name, and it is detected and reported if another tool needs to be run to restore routing information. The active cell is not automatically saved after the engineering change orders are applied. Instead, a user must manually save the active cell after the tool is run. The tool can work with three different name spaces: Verilog, VHDL and Avant! Verilog.
摘要翻译：实施工程变更单的工具和方法。该工具和方法规定，检查更改文件，计算等效的工程变更单并将其应用于活动单元格。工程变更单以预先确定的工具名称注册，如果需要运行另一个工具来恢复路由信息，则会检测并报告工程更改订单。应用工程更改订单后，活动单元格不会自动保存。相反，用户必须在工具运行后手动保存活动单元格。该工具可以使用三个不同的名称空间：Verilog，VHDL和Avant！ Verilog。

10. 发明申请

US20050097488A1 Method of partitioning an integrated circuit design for physical design verification 有权
标题翻译：分离用于物理设计验证的集成电路设计的方法
公开(公告)号：US20050097488A1
公开(公告)日：2005-05-05
申请号：US10697357
申请日：2003-10-29
申请人： Viswanathan Lakshmanan , Richard Blinne , Jonathan Kuppinger
发明人： Viswanathan Lakshmanan , Richard Blinne , Jonathan Kuppinger
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5081
摘要： A method of partitioning an integrated circuit design for physical design verification includes steps of: (a) receiving as input a representation of an integrated circuit design having a number of physical design layers; (b) receiving as input a composite run deck specifying rule checks to be performed on the integrated circuit design; (c) partitioning the composite run deck into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum; (d) parsing the representation of the integrated circuit design to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks; and (e) generating as output the filtered data deck for each of the partitioned run decks.
摘要翻译：对用于物理设计验证的集成电路设计进行分区的方法包括以下步骤：（a）作为输入接收具有多个物理设计层的集成电路设计的表示; （b）作为输入接收要在集成电路设计上执行的规则检查的复合运行平台; （c）将复合运行甲板划分为分区运行甲板，使得由每个分区运行甲板引用的物理设计层的数量是最小的; （d）解析集成电路设计的表示，以仅将每个分区运行平台所需的物理设计层过滤成用于每个分区运行平台的过滤数据卡; 和（e）生成用于每个分区运行平台的经过滤数据卡的输出。

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