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1. 发明授权

US07107559B2 Method of partitioning an integrated circuit design for physical design verification 有权
标题翻译：分离用于物理设计验证的集成电路设计的方法
公开(公告)号：US07107559B2
公开(公告)日：2006-09-12
申请号：US10697357
申请日：2003-10-29
申请人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
发明人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A method of partitioning an integrated circuit design for physical design verification includes steps of receiving as input a representation of an integrated circuit design having a number of physical design layers and a composite run deck specifying rule checks to be performed on the integrated circuit design. The composite run deck is partitioned into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum. The representation of the integrated circuit design is parsed to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks. The filtered data deck is generated as output for each of the partitioned run decks.
摘要翻译：对用于物理设计验证的集成电路设计进行分区的方法包括以下步骤：接收作为输入的具有多个物理设计层的集成电路设计的表示，以及指定要对集成电路设计执行的规则检查的复合运行层。复合运行甲板被划分为分区运行甲板，使得每个分区运行甲板引用的物理设计层的数量是最小的。解析集成电路设计的表示仅将每个分区运行平台所需的物理设计层过滤到每个分区运行卡的过滤数据卡。过滤的数据记录卡是为每个分区运行记录卡的输出生成的。

2. 发明授权

US07219317B2 Method and computer program for verifying an incremental change to an integrated circuit design 有权
标题翻译：用于验证集成电路设计的增量变化的方法和计算机程序
公开(公告)号：US07219317B2
公开(公告)日：2007-05-15
申请号：US10828408
申请日：2004-04-19
申请人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
发明人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A method and computer program product for verifying an incremental change to an integrated circuit design include receiving as input an integrated circuit design database and an engineering change order. Objects in the integrated circuit design database are identified and marked to indicate a current state of the integrated circuit design database. The engineering change order is applied to the integrated circuit design database, and the integrated circuit design database is analyzed to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order. Objects in the integrated circuit design database included in the list of incremental changes are identified and marked to distinguish objects in the integrated circuit design database that were changed from the current state. The marked integrated circuit design database distinguishing the objects that were changed from the current state is generated as output.
摘要翻译：用于验证集成电路设计的增量变化的方法和计算机程序产品包括接收集成电路设计数据库和工程变更顺序作为输入。集成电路设计数据库中的对象被识别并标记为指示集成电路设计数据库的当前状态。工程变更单适用于集成电路设计数据库，并对集成电路设计数据库进行分析，以生成由工程变更订单产生的集成电路设计数据库的增量变化清单。集成电路设计数据库中包含增量变化列表中的对象被识别并标记为区分集成电路设计数据库中与当前状态相对应的对象。标记的集成电路设计数据库将区分从当前状态改变的对象作为输出生成。

3. 发明授权

US07149989B2 Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design 有权
公开(公告)号：US07149989B2
公开(公告)日：2006-12-12
申请号：US10947498
申请日：2004-09-22
申请人： Viswanathan Lakshmanan , Alan Holesovsky , Lisa M. Miller , Jonathan P. Kuppinger
发明人： Viswanathan Lakshmanan , Alan Holesovsky , Lisa M. Miller , Jonathan P. Kuppinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits in the integrated circuit design and power distribution and input/output cell placement in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific rule deck.

4. 发明授权

US06216254B1 Integrated circuit design using a frequency synthesizer that automatically ensures testability 有权
标题翻译：使用频率合成器的集成电路设计，可自动确保可测试性
公开(公告)号：US06216254B1
公开(公告)日：2001-04-10
申请号：US09212769
申请日：1998-12-16
申请人： Michael S. Pesce , Kevin J. Gearhardt , Jonathan P. Kuppinger
发明人： Michael S. Pesce , Kevin J. Gearhardt , Jonathan P. Kuppinger
IPC分类号： G06F1750
CPC分类号： G01R31/31701
摘要： A system for designing integrated circuits that use frequency synthesizers to ensure testability. A testability circuit is added or connected to the frequency synthesizer that will receive allow the integrated circuit to operate in a system mode for normal function and in a test mode during testing. In the test mode, the testability circuit will inhibit the reset signal from initializing the integrated circuit until the frequency synthesizer has reached phase lock. The testability circuit may be implemented as a component in the frequency synthesizer cell in an ASIC design system such that anytime the frequency synthesizer is used, the integrated circuit is testable.
摘要翻译：用于设计使用频率合成器确保可测试性的集成电路的系统。可测试电路被添加或连接到频率合成器，接收允许集成电路在正常功能的系统模式下运行，并在测试期间在测试模式下运行。在测试模式下，可测试电路将禁止复位信号初始化集成电路直到频率合成器达到锁相。可测试性电路可以被实现为ASIC设计系统中的频率合成器单元中的组件，使得在使用频率合成器时，集成电路是可测试的。

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