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1. 发明申请

US20060136855A1 Method of implementing an engineering change order in an integrated circuit design by windows 有权
标题翻译：通过Windows实现集成电路设计中的工程变更顺序的方法
公开(公告)号：US20060136855A1
公开(公告)日：2006-06-22
申请号：US11015123
申请日：2004-12-17
申请人： Jason Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel Prevedel , Richard Blinne , Jonathan Kuppinger
发明人： Jason Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel Prevedel , Richard Blinne , Jonathan Kuppinger
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/04
摘要： A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.
摘要翻译：一种实现工程变更订单的方法包括以下步骤：（a）接收作为输入的集成电路设计; （b）作为输入接收集成电路设计的工程变更订单; （c）在集成电路设计中创建至少一个窗口，其包围由工程改变顺序引入的集成电路设计的变化，其中窗口由限定小于集成电路的整个区域的区域的坐标界定设计; （d）执行集成电路设计的路由，该路由排除不包括窗口的任何网络的路由; （e）将由窗口坐标限定的集成电路设计的副本中的区域替换为增量路由的结果以生成修订的集成电路设计; 和（f）产生经修订的集成电路设计的输出。

2. 发明申请

US20050235234A1 Method and computer program for verifying an incremental change to an integrated circuit design 有权
标题翻译：用于验证集成电路设计的增量变化的方法和计算机程序
公开(公告)号：US20050235234A1
公开(公告)日：2005-10-20
申请号：US10828408
申请日：2004-04-19
申请人： Viswanathan Lakshmanan , Richard Blinne , Jonathan Kuppinger
发明人： Viswanathan Lakshmanan , Richard Blinne , Jonathan Kuppinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A method and computer program product for verifying an incremental change to an integrated circuit design are described that include steps of: (a) receiving as input an integrated circuit design database; (b) receiving as input an engineering change order; (c) identifying and marking objects in the integrated circuit design database to indicate a current state of the integrated circuit design database; (d) applying the engineering change order to the integrated circuit design database; (e) analyzing the integrated circuit design database to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order; (f) identifying and marking objects in the integrated circuit design database included in the list of incremental changes to distinguish objects in the integrated circuit design database that were changed from the current state; and (g) streaming out the integrated circuit design database.
摘要翻译：描述了用于验证集成电路设计的增量变化的方法和计算机程序产品，其包括以下步骤：（a）作为输入接收集成电路设计数据库; （b）接收工程变更单作为输入; （c）识别和标记集成电路设计数据库中的对象，以指示集成电路设计数据库的当前状态; （d）将工程变更单应用于集成电路设计数据库; （e）分析集成电路设计数据库，以生成由工程变更订单产生的对集成电路设计数据库的增量变化的列表; （f）识别和标记增量变化列表中集成电路设计数据库中的对象，以区分从当前状态改变的集成电路设计数据库中的对象; 和（g）流出集成电路设计数据库。

3. 发明申请

US20050097488A1 Method of partitioning an integrated circuit design for physical design verification 有权
标题翻译：分离用于物理设计验证的集成电路设计的方法
公开(公告)号：US20050097488A1
公开(公告)日：2005-05-05
申请号：US10697357
申请日：2003-10-29
申请人： Viswanathan Lakshmanan , Richard Blinne , Jonathan Kuppinger
发明人： Viswanathan Lakshmanan , Richard Blinne , Jonathan Kuppinger
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5081
摘要： A method of partitioning an integrated circuit design for physical design verification includes steps of: (a) receiving as input a representation of an integrated circuit design having a number of physical design layers; (b) receiving as input a composite run deck specifying rule checks to be performed on the integrated circuit design; (c) partitioning the composite run deck into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum; (d) parsing the representation of the integrated circuit design to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks; and (e) generating as output the filtered data deck for each of the partitioned run decks.
摘要翻译：对用于物理设计验证的集成电路设计进行分区的方法包括以下步骤：（a）作为输入接收具有多个物理设计层的集成电路设计的表示; （b）作为输入接收要在集成电路设计上执行的规则检查的复合运行平台; （c）将复合运行甲板划分为分区运行甲板，使得由每个分区运行甲板引用的物理设计层的数量是最小的; （d）解析集成电路设计的表示，以仅将每个分区运行平台所需的物理设计层过滤成用于每个分区运行平台的过滤数据卡; 和（e）生成用于每个分区运行平台的经过滤数据卡的输出。

4. 发明申请

US20060095883A1 Method of automating place and route corrections for an integrated circuit design from physical design validation 有权
标题翻译：通过物理设计验证自动化集成电路设计的位置和路线校正方法
公开(公告)号：US20060095883A1
公开(公告)日：2006-05-04
申请号：US10977386
申请日：2004-10-29
申请人： Viswanathan Lakshmanan , Michael Josephides , Richard Blinne
发明人： Viswanathan Lakshmanan , Michael Josephides , Richard Blinne
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081
摘要： A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.
摘要翻译：一种用于自动校正集成电路设计中的错误的方法和计算机程序产品包括以下步骤：（a）执行集成电路设计的物理设计验证以验证是否符合一组设计规则; （b）生成通过物理设计验证检测到的设计规则违规的结果数据库; （c）从结果数据库中识别集成电路设计中的位置，以便根据后处理规则表进行设计更正，使设计更正的位置符合设计规则集; 和（d）在集成电路设计中实现设计校正。

5. 发明申请

US20060090144A1 Method of automating place and route corrections for an integrated circuit design from physical design validation 审中-公开
公开(公告)号：US20060090144A1
公开(公告)日：2006-04-27
申请号：US10975570
申请日：2004-10-27
申请人： Viswanathan Lakshmanan , Michael Josephides , Richard Blinne
发明人： Viswanathan Lakshmanan , Michael Josephides , Richard Blinne
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.

6. 发明授权

US07260803B2 Incremental dummy metal insertions 有权
标题翻译：增量的虚拟金属插入
公开(公告)号：US07260803B2
公开(公告)日：2007-08-21
申请号：US10683369
申请日：2003-10-10
申请人： Viswanathan Lakshmanan , Richard Blinne , Vikram Shrowty , Lena Montecillo
发明人： Viswanathan Lakshmanan , Richard Blinne , Vikram Shrowty , Lena Montecillo
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method and system for performing dummy metal insertion in design data for an integrated circuit is disclosed, wherein the design data includes dummy metal objects inserted by a dummy fill tool. After a portion of the design data is changed, a check is performed to determine whether any dummy metal objects intersect with any other objects in the design data. If so, the intersecting dummy metal objects are deleted from the design data, thereby avoiding having to rerun the dummy fill tool.
摘要翻译：公开了一种用于在集成电路的设计数据中执行虚拟金属插入的方法和系统，其中设计数据包括由虚拟填充工具插入的虚拟金属物体。在设计数据的一部分改变之后，执行检查以确定任何虚拟金属物体是否与设计数据中的任何其他对象相交。如果是这样，则从设计数据中删除相交的虚拟金属物体，从而避免重新运行虚拟填充工具。

7. 发明申请

US20060064656A1 Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design 有权
标题翻译：集成电路设计中的短信金属短路的早期物理设计验证和识别方法
公开(公告)号：US20060064656A1
公开(公告)日：2006-03-23
申请号：US10947498
申请日：2004-09-22
申请人： Viswanathan Lakshmanan , Alan Holesovsky , Lisa Miller , Jonathan Kuppinger
发明人： Viswanathan Lakshmanan , Alan Holesovsky , Lisa Miller , Jonathan Kuppinger
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits in the integrated circuit design and power distribution and input/output cell placement in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific rule deck.
摘要翻译：用于集成电路设计中的短信金属短路的早期物理设计验证和识别的方法和计算机程序产品包括以下步骤：（a）作为输入接收集成电路设计的表示; （b）作为输入接收指定要在集成电路设计上执行的规则检查的物理设计规则卡; （c）从物理设计规则甲板生成特定规则甲板，其中特定规则甲板仅包括专用于识别集成电路设计中的发短信的金属短路和电力分配以及输入/输出电池放置之一的物理设计规则集成电路设计; 和（d）从特定的规则层面对集成电路设计进行物理设计验证。

8. 发明授权

US08046726B2 Waiver mechanism for physical verification of system designs 失效
标题翻译：系统设计物理验证豁免机制
公开(公告)号：US08046726B2
公开(公告)日：2011-10-25
申请号：US12211238
申请日：2008-09-16
申请人： Viswanathan Lakshmanan , Michael Josephides , Lisa M. Miller
发明人： Viswanathan Lakshmanan , Michael Josephides , Lisa M. Miller
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081
摘要： A method of waiving verification failures is disclosed. The method generally includes the steps of (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, the circuit error files containing a plurality of circuit errors of the circuit designs, (B) generating a system error file by performing an additional physical verification on a system design, the system error file containing a plurality of system errors of the system design, the system design incorporating the circuit designs and (C) generating a valid error file by removing the circuit errors from the system error file, the valid error file containing a plurality of valid errors comprising a subset of the system errors.
摘要翻译：公开了一种放弃验证失败的方法。该方法通常包括以下步骤：（A）通过在多个电路设计上执行多个物理验证来产生多个电路错误文件，所述电路错误文件包含电路设计的多个电路错误，（B）产生系统错误文件通过在系统设计上执行附加物理验证，系统错误文件包含系统设计的多个系统错误，包含电路设计的系统设计，以及（C）通过去除电路来生成有效的错误文件来自系统错误文件的错误，有效的错误文件包含多个有效的错误，包括系统错误的子集。

9. 发明授权

US06775811B2 Chip design method for designing integrated circuit chips with embedded memories 失效
标题翻译：具有嵌入式存储器的集成电路芯片的芯片设计方法
公开(公告)号：US06775811B2
公开(公告)日：2004-08-10
申请号：US10151826
申请日：2002-05-22
申请人： Viswanathan Lakshmanan , Michael Josephides , Tom R. O'Brien , David A. Morgan
发明人： Viswanathan Lakshmanan , Michael Josephides , Tom R. O'Brien , David A. Morgan
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.
摘要翻译：一种用于设计具有一个或多个嵌入存储器的集成电路的电路设计方法。在逻辑设计中生成与每个包含的嵌入式存储器相关联的定时关键逻辑的布局。为所述每个包括的存储器生成增强的存储器边界。每个增强的存储器边界包括一个嵌入式存储器和相关联的所述定时关键逻辑。

10. 发明授权

US07007248B2 Method and apparatus for implementing engineering change orders 有权
标题翻译：实施工程变更单的方法和装置
公开(公告)号：US07007248B2
公开(公告)日：2006-02-28
申请号：US10439373
申请日：2003-05-15
申请人： Richard Blinne , Viswanathan Lakshmanan , Venugopalan Pranesan
发明人： Richard Blinne , Viswanathan Lakshmanan , Venugopalan Pranesan
IPC分类号： G06F17/50 , G06F19/00 , G06F7/00 , G06F17/30
CPC分类号： G06F17/5045 , Y10S707/99931 , Y10S707/99945
摘要： A tool and method for implementing engineering change orders. The tool and method provides that a change file is checked, equivalent engineering change orders are computed and applied to an active cell. The engineering change orders are registered with a pre-determined tool name, and it is detected and reported if another tool needs to be run to restore routing information. The active cell is not automatically saved after the engineering change orders are applied. Instead, a user must manually save the active cell after the tool is run. The tool can work with three different name spaces: Verilog, VHDL and Avant! Verilog.
摘要翻译：实施工程变更单的工具和方法。该工具和方法规定，检查更改文件，计算等效的工程变更单并将其应用于活动单元格。工程变更单以预先确定的工具名称注册，如果需要运行另一个工具来恢复路由信息，则会检测并报告工程更改订单。应用工程更改订单后，活动单元格不会自动保存。相反，用户必须在工具运行后手动保存活动单元格。该工具可以使用三个不同的名称空间：Verilog，VHDL和Avant！ Verilog。

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