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1. 发明授权

US07107559B2 Method of partitioning an integrated circuit design for physical design verification 有权
标题翻译：分离用于物理设计验证的集成电路设计的方法
公开(公告)号：US07107559B2
公开(公告)日：2006-09-12
申请号：US10697357
申请日：2003-10-29
申请人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
发明人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A method of partitioning an integrated circuit design for physical design verification includes steps of receiving as input a representation of an integrated circuit design having a number of physical design layers and a composite run deck specifying rule checks to be performed on the integrated circuit design. The composite run deck is partitioned into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum. The representation of the integrated circuit design is parsed to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks. The filtered data deck is generated as output for each of the partitioned run decks.
摘要翻译：对用于物理设计验证的集成电路设计进行分区的方法包括以下步骤：接收作为输入的具有多个物理设计层的集成电路设计的表示，以及指定要对集成电路设计执行的规则检查的复合运行层。复合运行甲板被划分为分区运行甲板，使得每个分区运行甲板引用的物理设计层的数量是最小的。解析集成电路设计的表示仅将每个分区运行平台所需的物理设计层过滤到每个分区运行卡的过滤数据卡。过滤的数据记录卡是为每个分区运行记录卡的输出生成的。

2. 发明授权

US07219317B2 Method and computer program for verifying an incremental change to an integrated circuit design 有权
标题翻译：用于验证集成电路设计的增量变化的方法和计算机程序
公开(公告)号：US07219317B2
公开(公告)日：2007-05-15
申请号：US10828408
申请日：2004-04-19
申请人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
发明人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A method and computer program product for verifying an incremental change to an integrated circuit design include receiving as input an integrated circuit design database and an engineering change order. Objects in the integrated circuit design database are identified and marked to indicate a current state of the integrated circuit design database. The engineering change order is applied to the integrated circuit design database, and the integrated circuit design database is analyzed to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order. Objects in the integrated circuit design database included in the list of incremental changes are identified and marked to distinguish objects in the integrated circuit design database that were changed from the current state. The marked integrated circuit design database distinguishing the objects that were changed from the current state is generated as output.
摘要翻译：用于验证集成电路设计的增量变化的方法和计算机程序产品包括接收集成电路设计数据库和工程变更顺序作为输入。集成电路设计数据库中的对象被识别并标记为指示集成电路设计数据库的当前状态。工程变更单适用于集成电路设计数据库，并对集成电路设计数据库进行分析，以生成由工程变更订单产生的集成电路设计数据库的增量变化清单。集成电路设计数据库中包含增量变化列表中的对象被识别并标记为区分集成电路设计数据库中与当前状态相对应的对象。标记的集成电路设计数据库将区分从当前状态改变的对象作为输出生成。

3. 发明授权

US07853901B2 Unified layer stack architecture 有权
标题翻译：统一层堆栈架构
公开(公告)号：US07853901B2
公开(公告)日：2010-12-14
申请号：US12109501
申请日：2008-04-25
申请人： Viswanathan Lakshmanan , Thomas R. O'Brien , Richard D. Blinne
发明人： Viswanathan Lakshmanan , Thomas R. O'Brien , Richard D. Blinne
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.
摘要翻译：一种用于生产数字集成电路设计系列的方法，其中家族具有最高级别的设计和至少一个较低级别的设计。最高水平的设计是首次生产。然后，在没有用户干预的编程计算系统中，自动处理最高级别的设计以选择性地移除至少一个预定的金属层。至少一个去除的金属层的最近的剩余覆盖层被自动映射到至少一个移除的金属层的最接近的剩余的下层，由此产生至少一个较低级设计。

4. 发明申请

US20090271755A1 Unified Layer Stack Architecture 有权
标题翻译：统一层堆栈架构
公开(公告)号：US20090271755A1
公开(公告)日：2009-10-29
申请号：US12109501
申请日：2008-04-25
申请人： Viswanathan Lakshmanan , Thomas R. O'Brien , Richard D. Blinne
发明人： Viswanathan Lakshmanan , Thomas R. O'Brien , Richard D. Blinne
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.
摘要翻译：一种用于生产数字集成电路设计系列的方法，其中家族具有最高级别的设计和至少一个较低级别的设计。最高水平的设计是首次生产。然后，在没有用户干预的编程计算系统中，自动处理最高级别的设计以选择性地移除至少一个预定的金属层。至少一个去除的金属层的最近的剩余覆盖层被自动映射到至少一个移除的金属层的最接近的剩余的下层，由此产生至少一个较低级设计。

5. 发明授权

US07302654B2 Method of automating place and route corrections for an integrated circuit design from physical design validation 有权
标题翻译：通过物理设计验证自动化集成电路设计的位置和路线校正方法
公开(公告)号：US07302654B2
公开(公告)日：2007-11-27
申请号：US10977386
申请日：2004-10-29
申请人： Viswanathan Lakshmanan , Michael Josephides , Richard D. Blinne
发明人： Viswanathan Lakshmanan , Michael Josephides , Richard D. Blinne
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.
摘要翻译：一种用于自动校正集成电路设计中的错误的方法和计算机程序产品包括以下步骤：（a）执行集成电路设计的物理设计验证以验证是否符合一组设计规则; （b）生成通过物理设计验证检测到的设计规则违规的结果数据库; （c）从结果数据库中识别集成电路设计中的位置，以便根据后处理规则表进行设计更正，使设计更正的位置符合设计规则集; 和（d）在集成电路设计中实现设计校正。

6. 发明授权

US07231626B2 Method of implementing an engineering change order in an integrated circuit design by windows 有权
标题翻译：通过Windows实现集成电路设计中的工程变更顺序的方法
公开(公告)号：US07231626B2
公开(公告)日：2007-06-12
申请号：US11015123
申请日：2004-12-17
申请人： Jason K. Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel W. Prevedel , Richard D. Blinne , Johathan P. Kuppinger
发明人： Jason K. Hoff , Viswanathan Lakshmanan , Michael Josephides , Daniel W. Prevedel , Richard D. Blinne , Johathan P. Kuppinger
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/04
摘要： A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.
摘要翻译：一种实现工程变更订单的方法包括以下步骤：（a）作为输入接收集成电路设计; （b）作为输入接收集成电路设计的工程变更订单; （c）在集成电路设计中创建至少一个窗口，其包围由工程改变顺序引入的集成电路设计的变化，其中窗口由限定小于集成电路的整个区域的区域的坐标界定设计; （d）执行集成电路设计的路由，该路由排除不包括窗口的任何网络的路由; （e）将由窗口坐标限定的集成电路设计的副本中的区域替换为增量路由的结果以生成修订的集成电路设计; 和（f）产生经修订的集成电路设计的输出。

7. 发明授权

US5521834A Method and apparatus for calculating dynamic power dissipation in CMOS integrated circuits 失效
标题翻译：用于计算CMOS集成电路中的动态功耗的方法和装置
公开(公告)号：US5521834A
公开(公告)日：1996-05-28
申请号：US159976
申请日：1993-11-30
申请人： Harold S. Crafts , Richard D. Blinne
发明人： Harold S. Crafts , Richard D. Blinne
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method and apparatus for approximating power dissipation using a computer-assisted engineering (CAE) system. Initially, a determination is made of the capacitive load for each cell in a netlist for the CMOS circuit, preferably from cell library data sheets. In addition, the capacitive loads of the interconnects between stages are estimated. A switching rate for each cell is then calculated using one of two alternative methods. The first method assumes that the patterns of input signals are statistically independent, and thus estimates the switching rate from the structure of the cell and the switching rates of the inputs. The second method uses known information concerning the relative times when the input signals are high or low to determine the switching rate of the cell. Once the switching rate is known, the output frequency for the cell can be determined. The power dissipation for each cell is then calculated by multiplying the output frequency by the capacitive load. The dynamic power dissipation for the circuit is determined by summing the power dissipation terms for each of the cells making up the netlist.
摘要翻译：一种使用计算机辅助工程（CAE）系统近似功耗的方法和装置。首先，确定CMOS电路的网表中的每个单元的容性负载，优选地从单元库数据表。此外，估计级之间的互连的容性负载。然后使用两种替代方法之一来计算每个单元的切换速率。第一种方法假设输入信号的模式在统计学上是独立的，因此从单元的结构和输入的开关速率估计开关速率。第二种方法使用关于输入信号高或低的相对时间的已知信息来确定单元的切换速率。一旦已知开关速率，就可以确定电池的输出频率。然后通过将输出频率乘以容性负载来计算每个单元的功耗。通过对构成网表的每个单元的功耗项求和来确定电路的动态功耗。

8. 发明授权

US6141631A Pulse rejection circuit model program and technique in VHDL 失效
标题翻译： VHDL中的脉冲抑制电路模型程序和技术
公开(公告)号：US6141631A
公开(公告)日：2000-10-31
申请号：US47877
申请日：1998-03-25
申请人： Richard D. Blinne , Sudhir K. Patel
发明人： Richard D. Blinne , Sudhir K. Patel
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method determines the behavior of a logic cell that receives input signals resulting in a narrow pulse or "glitch." If the pulse width of the output pulse is narrower than a pulse rejection period, the output pulse is rejected and is not propagated to subsequent logic cells connected to the output. The method employs a first internal logic cell model which is assigned an inertial delay function, and a second internal logic cell model which is assigned a transport delay function. In combination, the first and second logic cell models result in an effective propagation delay value, subject to the pulse rejection feature. An exemplary VHDL model is disclosed. A program product embodies a logic cell model in VHDL providing pulse rejection capabilities for output pulses with pulse width smaller than a pulse rejection period.
摘要翻译：一种方法确定接收输入信号导致窄脉冲或“毛刺”的逻辑单元的行为。如果输出脉冲的脉冲宽度比脉冲抑制周期窄，则输出脉冲被拒绝，不会传播到连接到输出端的后续逻辑单元。该方法采用分配有惯性延迟函数的第一内部逻辑单元模型和被分配有传输延迟函数的第二内部逻辑单元模型。结合起来，第一和第二逻辑单元模型导致有效的传播延迟值，受到脉冲抑制特性的影响。公开了示例性VHDL模型。程序产品体现了VHDL中的逻辑单元模型，为脉冲宽度小于脉冲抑制周期的输出脉冲提供脉冲抑制能力。

9. 发明授权

US5274568A Method of estimating logic cell delay time 失效
标题翻译：估计逻辑单元延迟时间的方法
公开(公告)号：US5274568A
公开(公告)日：1993-12-28
申请号：US623310
申请日：1990-12-05
申请人： Richard D. Blinne , Richard J. Holzer, Jr. , Timothy R. Ouellette , Rhea R. Ozman , Richard A. Laubhan , John Scott
发明人： Richard D. Blinne , Richard J. Holzer, Jr. , Timothy R. Ouellette , Rhea R. Ozman , Richard A. Laubhan , John Scott
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/5022
摘要： A method for approximating the delay time of an excitation through a logic cell using the summation of a base delay, which is a function of delay coefficients for the cell and the total output load capacitance of the cell, and a rise/fall time correction, which is determined from the output rise/fall time of the driving cell and the sensitivity of the analyzed cell to rise/fall time. Other corrections/compensating factors include a performance derating factor which accounts for the multiplicative effects of operating voltage, temperature and process.
摘要翻译：一种用于通过逻辑单元的激励的延迟时间近似的方法，所述延迟时间是基于单元的延迟系数和单元的总输出负载电容的函数的基本延迟的总和以及上升/下降时间校正，其根据驱动单元的输出上升/下降时间和分析单元的上升/下降时间的灵敏度确定。其他校正/补偿因素包括降低工作电压，温度和过程的乘积效应的性能降额因子。

10. 发明授权

US06662349B2 Method of repeater insertion for hierarchical integrated circuit design 有权
标题翻译：用于分层集成电路设计的中继器插入方法
公开(公告)号：US06662349B2
公开(公告)日：2003-12-09
申请号：US10086232
申请日：2002-02-27
申请人： David A. Morgan , Richard D. Blinne , James A. Jensen , Christopher J. Tremel
发明人： David A. Morgan , Richard D. Blinne , James A. Jensen , Christopher J. Tremel
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan for a parent macro at a parent level in a hierarchical circuit design; passing outline and pin locations from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan for the child macro at a child level in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing physical restrictions in the child macro from the child macro to the parent macro; determining a location for a cell at the parent level of the hierarchical circuit design in an area of the parent macro shared by the child macro in response to the physical restrictions passed from the child macro; passing physical constraints in the parent macro associated with placement and routing of the cell from the parent level to the child macro; and generating an abstract representation for the child macro at the child level that includes an area cut out of the child macro corresponding to the location of the cell.
摘要翻译：在分级集成电路中插入中继器的方法包括：在分级电路设计中，在父级别定义母宏的初始平面图; 将轮廓和引脚位置从父宏传递到与父宏共享公共区域的子宏; 响应于从父宏传送的轮廓和针位置，在分级电路设计中定义或修改子级别的子宏的平面图; 将子宏中的子宏中的物理限制从子宏传递到父宏; 响应于从所述子宏中传递的物理限制，在所述子宏宏共享的所述母宏的区域中确定所述分级电路设计的所述母级的单元的位置; 在与从父级别到子宏的单元的放置和路由相关联的父宏中传递物理约束; 以及生成子级别的子宏的抽象表示，该子宏包括从对应于该单元的位置的子宏中切出的区域。

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