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    • 1. 发明授权
    • Block cipher using key data merged with an intermediate block generated from a previous block
    • 使用与从先前块生成的中间块合并的密钥数据的块密码
    • US06459792B2
    • 2002-10-01
    • US09064469
    • 1998-04-22
    • Motoji OhmoriNatsume MatsuzakiMakoto TatebayashiMasakatsu Maruyama
    • Motoji OhmoriNatsume MatsuzakiMakoto TatebayashiMasakatsu Maruyama
    • H04L937
    • H04L9/0891H04L9/0637H04L9/0894H04L2209/38
    • A cryptographic processing apparatus for performing cryptographic processing using input data to generate output data is provided. The cryptographic processing apparatus includes a storage unit for storing chain data which is used for reflecting present cryptographic processing on next cryptographic processing, and for renewing the chain data each time cryptographic processing is performed, a merging unit for merging the chain data stored in the storage unit with the input data to generate merged data, and a main cryptographic processing unit for performing main cryptographic processing using the merged data to generate output data and for outputting intermediate data generated during a generation of the output data, wherein the storage unit renews the chain data by storing the intermediate data outputted by the main cryptographic processing unit as the new chain data, which is used for the next cryptographic processing.
    • 提供一种使用输入数据进行密码处理以产生输出数据的密码处理装置。 密码处理装置包括存储单元,用于存储链数据,用于反映当前密码处理对下一密码处理的处理,并且每次执行密码处理时更新链数据;合并单元,用于合并存储在存储器中的链数据 具有用于生成合并数据的输入数据的单元,以及主密码处理单元,用于使用合并数据执行主密码处理,以生成输出数据并输出在生成输出数据期间生成的中间数据,其中存储单元更新链 数据通过存储由主密码处理单元输出的中间数据作为用于下一个密码处理的新链接数据。
    • 4. 发明授权
    • Oversampling D/A converter using a bidirectional shift register
    • 使用双向移位寄存器的过采样D / A转换器
    • US5699064A
    • 1997-12-16
    • US509665
    • 1995-07-31
    • Shiro SakiyamaShiro DoshoMasakatsu MaruyamaGeorge HayashiSeizo InagakiAkira Matsuzawa
    • Shiro SakiyamaShiro DoshoMasakatsu MaruyamaGeorge HayashiSeizo InagakiAkira Matsuzawa
    • H03M3/04H03M1/78
    • H03M3/376H03M3/50
    • In an interpolative modulator, a signal which varies by only .+-.1 with one clock from a 1-bit quantizer is used as a shift-direction control signal. The shift-direction control signal is given to a bidirectional shift register. The bidirectional shift register shifts data based on the value of the shift-direction control signal that has been received. The output from the bidirectional shift register is given as a control signal to a resistive-ladder-type D/A converter. The resistive-ladder-type D/A converter outputs an analog potential corresponding to a switch selected by the above control signal. Therefore, if a delay difference occurs between any two bits, two adjacent switches are simply selected simultaneously, so that the output from the resistive-ladder-type D/A converter varies continuously. Consequently, there can be provided an oversampling D/A converter of resistive-ladder type with high accuracy and an increased yield, which is free from glitch (transiently generated noise).
    • 在内插调制器中,使用从1比特量化器的一个时钟仅变化+/- 1的信号作为移位方向控制信号。 移位方向控制信号被提供给双向移位寄存器。 双向移位寄存器基于接收到的移位方向控制信号的值来移位数据。 来自双向移位寄存器的输出作为电阻梯型D / A转换器的控制信号给出。 电阻梯型D / A转换器输出与由上述控制信号选择的开关相对应的模拟电位。 因此,如果任意两位之间发生延迟差,则两个相邻的开关被简单地同时选择,使得电阻梯型D / A转换器的输出连续变化。 因此,可以提供具有高精度和增加的产量的电梯梯型的过采样D / A转换器,其没有毛刺(瞬时产生的噪声)。
    • 9. 发明授权
    • Neural network circuit for adaptively controlling the coupling of neurons
    • 用于自适应控制神经元耦合的神经网络电路
    • US5452402A
    • 1995-09-19
    • US155865
    • 1993-11-23
    • Shiro SakiyamaMasakatsu MaruyamaHiroyuki NakahiraToshiyuki KoudaSusumu Maruno
    • Shiro SakiyamaMasakatsu MaruyamaHiroyuki NakahiraToshiyuki KoudaSusumu Maruno
    • G06F15/18G06N3/04G06N3/08G06N99/00G06T7/00G06F15/00
    • G06K9/62G06N3/08G06N3/082
    • In a multi-layered neural network circuit provided with an input layer having input vectors, an intermediate layer having networks in tree-like structure whose outputs are necessarily determined by the values of the input vectors and whose number corresponds to the number of the input vectors of the input layer, and an output layer having plural output units for integrating all outputs of the intermediate layer, provided are learning-time memories for memorizing the numbers of times at learning in paths between the intermediate layer and the respective output units, threshold processing circuits for threshold-processing the outputs of the leaning-time memories, and connection control circuits to be controlled by the outputs of the threshold processing circuits for controlling connection of paths between the intermediate layer and the output units. The outputs of the intermediate layer connected by the connection control circuits are summed in each output unit. Thus, the neural network circuit for recognizing an image or the like can execute recognition and learning of data to be recognized at high speed with small circuit size, and the recognition accuracy for unlearned data is high.
    • 在设置有具有输入向量的输入层的多层神经网络电路中,具有树状结构的网络的中间层,其输出必须由输入向量的值决定,其数量对应于输入向量的数量 以及输出层,具有用于积分中间层的所有输出的多个输出单元,所述输出层是用于存储中间层和各个输出单元之间的路径中学习次数的学习时间存储器,阈值处理 用于对倾斜时间存储器的输出进行阈值处理的电路和由用于控制中间层和输出单元之间的路径连接的阈值处理电路的输出来控制的连接控制电路。 由连接控制电路连接的中间层的输出在每个输出单元中相加。 因此,用于识别图像等的神经网络电路可以以较小的电路尺寸执行高速识别的数据的识别和学习,并且未被读取的数据的识别精度高。