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1. 发明授权

US5452402A Neural network circuit for adaptively controlling the coupling of neurons 失效
标题翻译：用于自适应控制神经元耦合的神经网络电路
公开(公告)号：US5452402A
公开(公告)日：1995-09-19
申请号：US155865
申请日：1993-11-23
申请人： Shiro Sakiyama , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Kouda , Susumu Maruno
发明人： Shiro Sakiyama , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Kouda , Susumu Maruno
IPC分类号： G06F15/18 , G06N3/04 , G06N3/08 , G06N99/00 , G06T7/00 , G06F15/00
CPC分类号： G06K9/62 , G06N3/08 , G06N3/082
摘要： In a multi-layered neural network circuit provided with an input layer having input vectors, an intermediate layer having networks in tree-like structure whose outputs are necessarily determined by the values of the input vectors and whose number corresponds to the number of the input vectors of the input layer, and an output layer having plural output units for integrating all outputs of the intermediate layer, provided are learning-time memories for memorizing the numbers of times at learning in paths between the intermediate layer and the respective output units, threshold processing circuits for threshold-processing the outputs of the leaning-time memories, and connection control circuits to be controlled by the outputs of the threshold processing circuits for controlling connection of paths between the intermediate layer and the output units. The outputs of the intermediate layer connected by the connection control circuits are summed in each output unit. Thus, the neural network circuit for recognizing an image or the like can execute recognition and learning of data to be recognized at high speed with small circuit size, and the recognition accuracy for unlearned data is high.
摘要翻译：在设置有具有输入向量的输入层的多层神经网络电路中，具有树状结构的网络的中间层，其输出必须由输入向量的值决定，其数量对应于输入向量的数量以及输出层，具有用于积分中间层的所有输出的多个输出单元，所述输出层是用于存储中间层和各个输出单元之间的路径中学习次数的学习时间存储器，阈值处理用于对倾斜时间存储器的输出进行阈值处理的电路和由用于控制中间层和输出单元之间的路径连接的阈值处理电路的输出来控制的连接控制电路。由连接控制电路连接的中间层的输出在每个输出单元中相加。因此，用于识别图像等的神经网络电路可以以较小的电路尺寸执行高速识别的数据的识别和学习，并且未被读取的数据的识别精度高。

2. 发明授权

US5621862A Information processing apparatus for implementing neural network 失效
标题翻译：用于实现神经网络的信息处理设备
公开(公告)号：US5621862A
公开(公告)日：1997-04-15
申请号：US281683
申请日：1994-07-28
申请人： Hiroyuki Nakahira , Masakatsu Maruyama , Shiro Sakiyama , Susumu Maruno , Toshiyuki Kouda , Masaru Fukuda
发明人： Hiroyuki Nakahira , Masakatsu Maruyama , Shiro Sakiyama , Susumu Maruno , Toshiyuki Kouda , Masaru Fukuda
IPC分类号： G06K9/66 , G06N3/08 , G06N3/10 , G06F15/18
CPC分类号： G06K9/00986 , G06K9/6267 , G06N3/082 , G06N3/10
摘要： In an information processing apparatus for implementing a neural network, if an input vector is inputted to a calculating unit, a neuron which responds to the input vector is retrieved in accordance with network interconnection information stored in a first storage unit and the neuron number indicating the retrieved neuron is written in a first register. The calculating unit reads out the internal information of the neuron stored in a second storage unit by using the neuron number, writes it in a second register, and calculates the sum of products of the outputs of the neurons and the connection loads of synapses connected to the neurons. By repeating the sequence of operations by the number of times corresponding to the total number of input vectors, a recognition process is executed. The neural network can easily be expanded by rewriting the contents of the first and second storage units.
摘要翻译：在用于实现神经网络的信息处理装置中，如果将输入向量输入到计算单元，则根据存储在第一存储单元中的网络互连信息来检索响应于输入向量的神经元，并且指示检索到的神经元被写入第一个寄存器。计算单元通过使用神经元号读取存储在第二存储单元中的神经元的内部信息，将其写入第二寄存器，并且计算神经元的输出和连接到的突触的连接负载的乘积之和神经元。通过将操作序列重复与输入向量的总数相对应的次数，执行识别处理。可以通过重写第一和第二存储单元的内容来容易地扩展神经网络。

3. 发明授权

US5636327A Neural network circuit 失效
标题翻译：神经网络电路
公开(公告)号：US5636327A
公开(公告)日：1997-06-03
申请号：US409949
申请日：1995-03-23
申请人： Hiroyuki Nakahira , Shiro Sakiyama , Masakatsu Maruyama , Susumu Maruno
发明人： Hiroyuki Nakahira , Shiro Sakiyama , Masakatsu Maruyama , Susumu Maruno
IPC分类号： G06N3/063 , G06F15/18
CPC分类号： G06K9/4628 , G06K9/00986 , G06N3/063
摘要： In a multilayered neural network for recognizing and processing characteristic data of images and the like by carrying out network arithmetical operations, characteristic data memories store the characteristic data of the layers. Coefficient memories store respective coupling coefficients of the layers other than the last layer. A weight memory stores weights of neurons of the last layer. Address converters carry out arithmetical operations to find out addresses of nets of the network whose coupling coefficients are significant. A table memory outputs a total coupling coefficient obtained by inter-multiplying the significant coupling coefficients read out from the coefficient memories of the layers. A cumulative operation unit performs cumulative additions of the product of the total coupling coefficient times the weight of the weight memory. Arithmetical operations are carried out only on particular nets with a significant coupling coefficient value. The speed of operation and recognition can be improved.
摘要翻译：在通过进行网络算术运算来识别和处理图像等的特征数据的多层神经网络中，特征数据存储器存储层的特征数据。系数存储器存储不同于最后层的层的相应耦合系数。体重记忆存储最后层的神经元的权重。地址转换器进行算术运算，找出耦合系数很大的网络网络地址。表存储器输出通过相互乘以从层的系数存储器读出的有效耦合系数而获得的总耦合系数。累积操作单元执行总耦合系数乘以权重存储器的权重的乘积的累积加法。仅对具有显着耦合系数值的特定网络进行算术运算。可以提高运行和识别的速度。

4. 发明授权

US5550544A Signal converter, noise shaper, AD converter and DA converter 失效
标题翻译：信号转换器，噪声整形器，AD转换器和DA转换器
公开(公告)号：US5550544A
公开(公告)日：1996-08-27
申请号：US200493
申请日：1994-02-23
申请人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Shono , Akira Matsuzawa
发明人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Shono , Akira Matsuzawa
IPC分类号： H03M3/00 , H03M1/00
CPC分类号： H03M3/424 , H03M3/456
摘要： The present invention provides a first-order delta-sigma AD converter adapted to conduct noise shaping and having a quantizer arranged such that, when the amplitude of an input signal entered into the quantizer is small, the amplitude of a difference signal between the input signal entered into the quantizer and an output signal therefrom, is small. It is therefore possible to achieve an efficient AD- or DA-converter reduced in power consumption, which satisfies the transmission characteristics of the specifications of CCITT G.714 based on a method of PCM-encoding an audio frequency band signal stipulated in the specifications of CCITT G.711.
摘要翻译：本发明提供了一种适用于进行噪声整形并具有量化器的一级Δ-ΣAD转换器，其被布置为使得当输入到量化器的输入信号的幅度较小时，输入信号之间的差信号的幅度进入量化器并且其输出信号很小。因此，可以实现功率消耗降低的有效的AD转换器或DA转换器，该功率消耗满足CCITT G.714的规格的传输特性，该方法基于对编码 CCITT G.711。

5. 发明授权

US6067536A Neural network for voice and pattern recognition 失效
标题翻译：用于语音和模式识别的神经网络
公开(公告)号：US6067536A
公开(公告)日：2000-05-23
申请号：US864938
申请日：1997-05-29
申请人： Masakatsu Maruyama , Hiroyuki Nakahira , Masaru Fukuda , Shiro Sakiyama
发明人： Masakatsu Maruyama , Hiroyuki Nakahira , Masaru Fukuda , Shiro Sakiyama
IPC分类号： G06K9/66 , G06N3/063 , G06E1/00
CPC分类号： G06K9/6267 , G06K9/00986 , G06N3/063
摘要： A neural network circuit for performing a processing of recognizing voices, images and the like comprises a weight memory for holding a lot of weight values (initial weight values) which correspond to a plurality of input terminals of each of a plurality of neurons forming a neural network and have been initially learned, and a difference value memory for storing difference values between the weight values of the weight memory and additionally learned weight values. The weight memory is formed by a ROM. The difference value memory is formed by a SRAM, for example. During operation of recognizing input data, the initial weight values of the weight memory and the difference values of the difference value memory are added together. The added weight values are used to calculate an output value of each neuron of an output layer. Accordingly, the initial weight values can be additionally learned at a high speed by existence of the difference value memory having a small capacity. Thus, new numerals, characters and the like can be recognized well without error.
摘要翻译：用于执行识别语音，图像等的处理的神经网络电路包括用于保存与形成神经元的多个神经元中的每一个的多个输入端相对应的大量权重值（初始权重值）的权重存储器网络并且已经被初步了解，以及差值存储器，用于存储权重存储器的权重值和附加学习的权重值之间的差值。重量存储器由ROM形成。差值存储器例如由SRAM形成。在识别输入数据的操作期间，将加权存储器的初始权重值和差值存储器的差值相加在一起。加权重值用于计算输出层每个神经元的输出值。因此，通过存在具有小容量的差值存储器，可以高速地附加地学习初始权重值。因此，可以很好地识别新的数字，字符等。

6. 发明授权

US5136662A Image processor for sequential processing of successive regions of an image 失效
标题翻译：用于连续处理图像的连续区域的图像处理器
公开(公告)号：US5136662A
公开(公告)日：1992-08-04
申请号：US449194
申请日：1989-12-13
申请人： Masakatsu Maruyama , Shiro Sakiyama , Hiroyuki Nakahira , Yoshitaka Kitao , Toshiyuki Araki
发明人： Masakatsu Maruyama , Shiro Sakiyama , Hiroyuki Nakahira , Yoshitaka Kitao , Toshiyuki Araki
IPC分类号： G06T5/20
CPC分类号： G06T5/20
摘要： A local image processor is configured as a plurality of image processor elements each having a local image memory, and a single shift register circuit for supplying to the local image memories successive local images formed of an array of pixels of a source image. Each processor element includes a register holding a count value indicating the position within the source image of data that are currently being processed by that element, and the processor elements also include mutually interconnected registers whereby intermediate computation results obtained by one processor element can be utilized by another element during parallel processing operation.
摘要翻译：局部图像处理器被配置为多个具有本地图像存储器的图像处理器元件，以及单个移位寄存器电路，用于向源图像的像素阵列形成的连续的局部图像提供给局部图像存储器。每个处理器元件包括一个寄存器，该寄存器保存指示当前由该元件处理的数据的源图像内的位置的计数值，并且处理器元件还包括相互互连的寄存器，由此可以利用由一个处理器元件获得的中间计算结果并行处理操作中的另一个元素。

7. 发明授权

US5699064A Oversampling D/A converter using a bidirectional shift register 失效
标题翻译：使用双向移位寄存器的过采样D / A转换器
公开(公告)号：US5699064A
公开(公告)日：1997-12-16
申请号：US509665
申请日：1995-07-31
申请人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , George Hayashi , Seizo Inagaki , Akira Matsuzawa
发明人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , George Hayashi , Seizo Inagaki , Akira Matsuzawa
IPC分类号： H03M3/04 , H03M1/78
CPC分类号： H03M3/376 , H03M3/50
摘要： In an interpolative modulator, a signal which varies by only .+-.1 with one clock from a 1-bit quantizer is used as a shift-direction control signal. The shift-direction control signal is given to a bidirectional shift register. The bidirectional shift register shifts data based on the value of the shift-direction control signal that has been received. The output from the bidirectional shift register is given as a control signal to a resistive-ladder-type D/A converter. The resistive-ladder-type D/A converter outputs an analog potential corresponding to a switch selected by the above control signal. Therefore, if a delay difference occurs between any two bits, two adjacent switches are simply selected simultaneously, so that the output from the resistive-ladder-type D/A converter varies continuously. Consequently, there can be provided an oversampling D/A converter of resistive-ladder type with high accuracy and an increased yield, which is free from glitch (transiently generated noise).
摘要翻译：在内插调制器中，使用从1比特量化器的一个时钟仅变化+/- 1的信号作为移位方向控制信号。移位方向控制信号被提供给双向移位寄存器。双向移位寄存器基于接收到的移位方向控制信号的值来移位数据。来自双向移位寄存器的输出作为电阻梯型D / A转换器的控制信号给出。电阻梯型D / A转换器输出与由上述控制信号选择的开关相对应的模拟电位。因此，如果任意两位之间发生延迟差，则两个相邻的开关被简单地同时选择，使得电阻梯型D / A转换器的输出连续变化。因此，可以提供具有高精度和增加的产量的电梯梯型的过采样D / A转换器，其没有毛刺（瞬时产生的噪声）。

8. 发明授权

US5278781A Digital signal processing system 失效
标题翻译：数字信号处理系统
公开(公告)号：US5278781A
公开(公告)日：1994-01-11
申请号：US51273
申请日：1993-04-23
申请人： Kunitoshi Aono , Masaki Toyokura , Shiro Sakiyama , Toshiyuki Araki , Masakatsu Maruyama
发明人： Kunitoshi Aono , Masaki Toyokura , Shiro Sakiyama , Toshiyuki Araki , Masakatsu Maruyama
IPC分类号： G06F7/544 , G06F17/10 , G06F7/38
CPC分类号： G06F7/5443 , G06F17/10 , G06F2207/3884
摘要： A digital signal processing system includes a plurality of multiplier/accumulators for executing a pipeline processing operation. Each of the plurality of multiplier/accumulators includes a multiplication part and an addition part. The multiplication parts includes N pipeline registers for storing N intermediate outputs of a multiplier. The addition part includes a Wallace tree transformation unit for transforming a sum of N+1 inputs into two transformation outputs, and an adder for adding the two transformation outputs. The N+1 inputs includes the N intermediate outputs from the multiplication part and the one addition output from the adder.
摘要翻译：数字信号处理系统包括用于执行流水线处理操作的多个乘法器/累加器。多个乘法器/累加器中的每一个包括乘法部分和加法部分。乘法部分包括用于存储乘法器的N个中间输出的N个流水线寄存器。加法部分包括用于将N + 1个输入的和转换为两个变换输出的华莱士树变换单元和用于将两个变换输出相加的加法器。 N + 1输入包括来自乘法部分的N个中间输出和来自加法器的一个相加输出。

9. 发明授权

US5383145A Digital filter and digital signal processing system 失效
标题翻译：数字滤波器和数字信号处理系统
公开(公告)号：US5383145A
公开(公告)日：1995-01-17
申请号：US136024
申请日：1993-10-14
申请人： Shiro Sakiyama , Masakatsu Maruyama
发明人： Shiro Sakiyama , Masakatsu Maruyama
IPC分类号： G06F17/10 , H03H17/06 , G06F15/31
CPC分类号： H03H17/06 , G06F17/10
摘要： In a direct type of finite impulse response (FIR) digital filter, direct type digital filters consisting a plurality of taps are used as a construction element of a digital filter. A pipeline structure is constructed between cascaded construction elements, and the sum and carry signals of the multi-input addition in the midst of the addition operation are transferred between cascaded construction elements. The number of gates, dissipation power, chip area and the like can be decreased as compared with a prior art inverted type digital filter. Further, a digital signal processing system such as a waveform equalizing system can be constructed using a direct type digital filter as mentioned above, and such a system includes a selector for selecting the output of the digital filter and an output in the midst of the delays in the digital filter.
摘要翻译：在有限脉冲响应（FIR）数字滤波器的直接类型中，使用由多个抽头组成的直接型数字滤波器作为数字滤波器的构造元件。在级联构造元件之间构造管道结构，并且在加法运算中间的多输入加法的和和进位信号在级联构造元件之间传递。与现有技术的倒置型数字滤波器相比，门数，耗散功率，芯片面积等可以减少。此外，可以使用如上所述的直接型数字滤波器来构造诸如波形均衡系统的数字信号处理系统，并且这样的系统包括用于选择数字滤波器的输出的选择器和在延迟中的输出在数字滤镜中。

10. 发明授权

US5751142A Reference voltage supply circuit and voltage feedback circuit 失效
标题翻译：参考电压电路和电压反馈电路
公开(公告)号：US5751142A
公开(公告)日：1998-05-12
申请号：US795906
申请日：1997-03-04
申请人： Shiro Dosho , Shiro Sakiyama , Masakatsu Maruyama , Masatoshi Matsushita , Koji Mochizuki
发明人： Shiro Dosho , Shiro Sakiyama , Masakatsu Maruyama , Masatoshi Matsushita , Koji Mochizuki
IPC分类号： G05F3/24 , G05F3/26 , G05F3/20
CPC分类号： G05F3/247 , G05F3/262 , Y10S323/901
摘要： A reference voltage output terminal of first and second reference voltage generating circuits is connected to a first current input terminal of a current mirror circuit of an operational amplifier by a diode element. At the time of start-up, a reference voltage generated on the reference voltage output terminal is 0 V. Consequently, a current flows to the diode element and an offset voltage Voff is generated on the operational amplifier so that a malfunction point is caused to disappear. Accordingly, in the case where a normal operation point on which a reference voltage having an expected value is generated and a malfunction point on which an operation is stabilized with a reference voltage having a value less than the expected value are present, the generated reference voltage is raised at the time of start-up, passes through the malfunction point to reach an expected voltage value on the normal operation point and becomes stabilized. In this state, the diode element is cut off so that the offset voltage Voff is caused to disappear.
摘要翻译：第一和第二参考电压产生电路的参考电压输出端通过二极管元件连接到运算放大器的电流镜电路的第一电流输入端。在启动时，在基准电压输出端子上产生的基准电压为0V。因此，电流流向二极管元件，并在运算放大器上产生偏移电压Voff，使得产生故障点消失。因此，在存在具有预期值的基准电压的正常工作点和存在具有小于预期值的参考电压使运行稳定的故障点的情况下，产生的基准电压在启动时升高，通过故障点达到正常工作点的预期电压值并稳定。在这种状态下，二极管元件被切断，使偏移电压Voff消失。

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