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1. 发明授权

US06696342B1 Small emitter and base-collector bi-polar transistor 有权
标题翻译：小型发射极和基极集电极双极晶体管
公开(公告)号：US06696342B1
公开(公告)日：2004-02-24
申请号：US09882936
申请日：2001-06-15
申请人： Mohamed N. Darwish , Alexei Sadovinkov , Reda Razouk
发明人： Mohamed N. Darwish , Alexei Sadovinkov , Reda Razouk
IPC分类号： H01L218222
CPC分类号： H01L29/66287 , H01L21/8249 , H01L29/1004 , H01L29/66242 , H01L29/732
摘要： In a high speed BJT device, the method for producing the device includes forming a self-aligned BJT through the use of a single mask by making use of a single layer of polysilicon. The method includes forming a window in the polysilicon to define a base poly region and an emitter poly region. An underlying oxide/nitride stack is etched in a two etch process to define base and emitter regions for growing a small base and a small emitter. This displays small base-collector and base-emitter junction regions to reduce the capacitance.
摘要翻译：在高速BJT器件中，用于制造器件的方法包括通过使用单层多晶硅来使用单个掩模形成自对准BJT。该方法包括在多晶硅中形成窗口以限定基极多晶区域和发射极多晶区域。在两个蚀刻工艺中蚀刻下面的氧化物/氮化物叠层以限定用于生长小基极和小发射极的基极和发射极区域。这显示了小的基极集电极和基极 - 发射极结区域以减小电容。

2. 发明授权

US06475848B1 Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor 有权
标题翻译：多晶硅边缘，低功耗，高频双极晶体管和形成晶体管的方法
公开(公告)号：US06475848B1
公开(公告)日：2002-11-05
申请号：US09882600
申请日：2001-06-15
申请人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
发明人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
IPC分类号： H01L218238
CPC分类号： H01L29/66287 , H01L29/732
摘要： A low-power high-frequency bipolar transistor is formed to have a small self-aligned base region that reduces the base-to-collector capacitance, and small self-aligned base and emitter contacts that reduce the base-to-emitter capacitance and the base resistance. The base and emitter contacts are formed to have sub-lithographic feature sizes.
摘要翻译：低功率高频双极晶体管形成为具有减小基极到集电极电容的小的自对准基极区域，以及减小基极 - 发射极电容的小的自对准基极和发射极触点，以及基座阻力。基极和发射极触点形成为具有亚光刻特征尺寸。

3. 发明授权

US06380017B1 Polysilicon-edge, base-emitter super self-aligned, low-power, high-frequency bipolar transistor and method of forming the transistor 有权
标题翻译：多晶硅边缘，基极 - 发射极超自对准，低功耗，高频双极晶体管和形成晶体管的方法
公开(公告)号：US06380017B1
公开(公告)日：2002-04-30
申请号：US09882859
申请日：2001-06-15
申请人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
发明人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
IPC分类号： H01L218238
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/41708 , H01L29/732
摘要： A low-power high-frequency bipolar transistor is formed to have a small self-aligned intrinsic base region, and small self-aligned extrinsic base and emitter regions that contact the intrinsic base region. The small regions reduce the base resistance, the base-to-collector capacitance, and the base-to-emitter capacitance.
摘要翻译：低功率高频双极晶体管被形成为具有小的自对准本征基极区域，以及接触本征基极区域的小的自对准的非本征基极和发射极区域。小区域降低了基极电阻，基极 - 集电极电容和基极 - 发射极电容。

4. 发明授权

US06603188B1 Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor 有权
公开(公告)号：US06603188B1
公开(公告)日：2003-08-05
申请号：US10207628
申请日：2002-07-29
申请人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
发明人： Mohamed N. Darwish , Alexei Sadovnikov , Reda Razouk
IPC分类号： H01L27082
CPC分类号： H01L29/66287 , H01L29/732
摘要： A low-power high-frequency bipolar transistor is formed to have a small self-aligned base region that reduces the base-to-collector capacitance, and small self-aligned base and emitter contacts that reduce the base-to-emitter capacitance and the base resistance. The base and emitter contacts are formed to have sub-lithographic feature sizes.

5. 发明申请

US20100065964A1 COPPER-TOPPED INTERCONNECT STRUCTURE THAT HAS THIN AND THICK COPPER TRACES AND METHOD OF FORMING THE COPPER-TOPPED INTERCONNECT STRUCTURE 有权
标题翻译：具有较薄铜箔铜箔的铜箔互连结构及形成铜箔互连结构的方法
公开(公告)号：US20100065964A1
公开(公告)日：2010-03-18
申请号：US12283852
申请日：2008-09-15
申请人： Abdalla Aly Naem , Reda Razouk
发明人： Abdalla Aly Naem , Reda Razouk
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/76885 , H01L21/76852 , H01L23/5283 , H01L23/53238 , H01L24/14 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05568 , H01L2224/0557 , H01L2224/05571 , H01L2224/05647 , H01L2224/1403 , H01L2924/00014
摘要： A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.
摘要翻译：铜顶互连结构允许高密度设计区域的组合，其具有可以满足紧密堆叠的薄和窄铜迹线的低电流要求以及具有高电流要求的低密度设计区域，其可以满足更多在相同的芯片上，宽间隔的厚和宽的铜迹线。

6. 发明授权

US4455325A Method of inducing flow or densification of phosphosilicate glass for integrated circuits 失效
标题翻译：诱导集成电路磷硅玻璃流动或致密化的方法
公开(公告)号：US4455325A
公开(公告)日：1984-06-19
申请号：US456200
申请日：1983-01-07
申请人： Reda Razouk
发明人： Reda Razouk
IPC分类号： H01L21/3105 , H01L21/60 , H01L21/768 , H05K1/03 , H05K3/28 , H01L21/02
CPC分类号： H01L21/76897 , H01L21/3105 , H01L21/76819 , H05K1/0306 , H05K3/28
摘要： Phosphorus-doped silicon oxide glass is flowed on an integrated circuit by raising the pressure in which that integrated circuit is placed above atmospheric for a selected period of time and heating said phosphosilicate glass to a selected temperature sufficient to cause said glass to flow at said pressure. The atmosphere in which the device is placed includes moisture to enhance the flow of the glass at temperatures substantially beneath those at which dopants in the underlying integrated circuit move. The result is that the electrical characteristics of the integrated circuit are not substantially altered during glass flow.
摘要翻译：磷掺杂氧化硅玻璃通过将集成电路放置在高于大气压的选定时间段的压力下流动在集成电路上，并将所述磷硅玻璃加热至足以使所述玻璃在所述压力下流动的选定温度。设备放置的气氛包括水分，以在基本上低于下层集成电路中的掺杂剂移动的温度的温度下增加玻璃的流动。结果是，在玻璃流动期间，集成电路的电气特性基本上不被改变。

7. 发明授权

US07709956B2 Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure 有权
标题翻译：具有薄而粗铜迹线的铜顶互连结构和形成铜顶互连结构的方法
公开(公告)号：US07709956B2
公开(公告)日：2010-05-04
申请号：US12283852
申请日：2008-09-15
申请人： Abdalla Aly Naem , Reda Razouk
发明人： Abdalla Aly Naem , Reda Razouk
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/053 , H01L23/12 , H01L27/10 , H01L29/74
CPC分类号： H01L21/76885 , H01L21/76852 , H01L23/5283 , H01L23/53238 , H01L24/14 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05568 , H01L2224/0557 , H01L2224/05571 , H01L2224/05647 , H01L2224/1403 , H01L2924/00014
摘要： A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.
摘要翻译：铜顶互连结构允许高密度设计区域的组合，其具有可以满足紧密堆叠的薄和窄铜迹线的低电流要求以及具有高电流要求的低密度设计区域，其可以满足更多在相同的芯片上，宽间隔的厚和宽的铜迹线。

8. 发明授权

US07067895B1 Color imager cell with transistors formed under the photodiodes 有权
标题翻译：具有晶体管的彩色成像器单元，其形成在光电二极管下
公开(公告)号：US07067895B1
公开(公告)日：2006-06-27
申请号：US10340165
申请日：2003-01-10
申请人： Reda Razouk
发明人： Reda Razouk
IPC分类号： H01L31/06
CPC分类号： H01L27/14647 , H01L27/14632 , H01L27/14687 , H01L27/14689
摘要： An imaging cell and a method of forming the imaging cell are disclosed. The imaging cell includes a first transistor that has source, a drain, and a gate, and a second transistor that has a source, a drain, and a gate connected to the source of the first transistor. In addition, the cell has a photodiode that is partially formed over the source of the second transistor.
摘要翻译：公开了一种成像单元及其形成方法。成像单元包括具有源极，漏极和栅极的第一晶体管，以及具有连接到第一晶体管的源极的源极，漏极和栅极的第二晶体管。此外，电池具有部分地形成在第二晶体管的源极上的光电二极管。

9. 发明授权

US06365447B1 High-voltage complementary bipolar and BiCMOS technology using double expitaxial growth 失效
标题翻译：高电压互补双极和BiCMOS技术采用双外延生长
公开(公告)号：US06365447B1
公开(公告)日：2002-04-02
申请号：US09005786
申请日：1998-01-12
申请人： Francois Hèbert , Datong Chen , Reda Razouk
发明人： Francois Hèbert , Datong Chen , Reda Razouk
IPC分类号： H01L218238
CPC分类号： H01L21/84 , H01L21/8249 , H01L27/1203
摘要： A method of making high voltage complementary bipolar and BiCMOS devices on a common substrate. The bipolar devices are vertical NPN and PNP transistors having the same structure. The fabrication process utilizes trench isolation and thus is scalable. The process uses two epitaxial silicon layers to form the high voltage NPN collector, with the PNP collector formed from a p-well diffused into the two epitaxial layers. The collector contact resistance is minimized by the use of sinker up/down structures formed at the interface of the two epitaxial layers. The process minimizes the thermal budget and therefore the up diffusion of the NPN and PNP buried layers. This maximizes the breakdown voltage at the collector-emitter junction for a given epitaxial thickness. The epitaxial layers may be doped as required depending upon the specifications for the high voltage NPN device. The process is compatible with the fabrication of low voltage devices, which can be formed by placing the sinker regions under the emitter region. The thicknesses of the two epitaxial layers may be adjusted as required depending upon the specifications for the low voltage devices.
摘要翻译：在公共衬底上制造高电压互补双极和BiCMOS器件的方法。双极器件是具有相同结构的垂直NPN和PNP晶体管。制造工艺利用沟槽隔离，因此是可扩展的。该工艺使用两个外延硅层来形成高压NPN集电极，PNP集电极由扩散到两个外延层中的p阱形成。通过使用在两个外延层的界面处形成的沉降片上/下结构来最小化集电极接触电阻。该过程使热预算最小化，因此最小化NPN和PNP埋层的向上扩散。对于给定的外延厚度，这使集电极 - 发射极结处的击穿电压最大化。外延层可以根据需要掺杂，这取决于高压NPN器件的规格。该工艺与低电压器件的制造兼容，这可以通过将沉降片区域放置在发射极区域下而形成。根据低电压器件的规格，可以根据需要调整两个外延层的厚度。

10. 发明授权

US06730969B1 Radiation hardened MOS transistor 有权
标题翻译：辐射硬化MOS晶体管
公开(公告)号：US06730969B1
公开(公告)日：2004-05-04
申请号：US10185927
申请日：2002-06-27
申请人： Gobi R. Padmanabhan , Visvamohan Yegnashankaran , Reda Razouk
发明人： Gobi R. Padmanabhan , Visvamohan Yegnashankaran , Reda Razouk
IPC分类号： H01L2362
CPC分类号： H01L29/4238 , H01L23/4824 , H01L29/0692 , H01L2924/0002 , H01L2924/00
摘要： The drain-to-source field leakage current and the device-to-device field leakage current that are caused by radiation-induced hole trapping in the field oxide region are reduced in the present invention by forming the source and drain regions a distance apart from the edge of the field oxide region.
摘要翻译：在本发明中，通过形成源极和漏极区域的距离减小了在场氧化物区域中由辐射诱发的空穴俘获引起的漏 - 源场漏电流和器件到器件场漏电流场氧化物区域的边缘。

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