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1. 发明授权

US06720811B2 Semiconductor device with delay correction function 失效
标题翻译：具有延迟校正功能的半导体器件
公开(公告)号：US06720811B2
公开(公告)日：2004-04-13
申请号：US10193251
申请日：2002-07-12
申请人： Minobu Yazawa , Shinichi Nakagawa , Yasushi Wada
发明人： Minobu Yazawa , Shinichi Nakagawa , Yasushi Wada
IPC分类号： H03L700
CPC分类号： H03K5/135 , G06F1/10 , H03K5/133 , H03K2005/00078
摘要： A semiconductor device includes a delay amount measuring unit, multiple delay sections and a correction signal generating unit. The delay amount measuring unit for measures an actual delay amount corresponding to a specified delay amount by supplying a clock signal with a known period to multiple 1-ns-delay strings with a preassigned delay amount, and by detecting phase variations of the clock signal by the 1-ns-delay strings. The delay sections includes a delay string capable of freely adjusting a connection number of its delay elements. The correction signal generating unit generates a correction signal for enabling each of the delay sections to correct the connection number of the delay strings such that each delay section has a desired delay amount, in accordance with the actual delay amount corresponding to the specified delay amount and measured by the delay measuring unit.
摘要翻译：半导体器件包括延迟量测量单元，多个延迟部分和校正信号生成单元。延迟量测量单元，用于通过向具有预分配的延迟量的多个1-ns延迟串提供具有已知周期的时钟信号，并且通过检测时钟信号的相位变化来检测相应于指定延迟量的实际延迟量， 1 ns延迟字符串。延迟部分包括能够自由地调节其延迟元件的连接数量的延迟串。校正信号生成单元根据与规定的延迟量对应的实际延迟量，生成用于使每个延迟部分能够校正延迟串的连接数，使得每个延迟部分具有期望的延迟量的校正信号，以及由延迟测量单元测量。

2. 发明授权

US5677860A Overflow and underflow processing circuit of a binary adder 失效
标题翻译：二进制加法器的溢出和下溢处理电路
公开(公告)号：US5677860A
公开(公告)日：1997-10-14
申请号：US324643
申请日：1994-10-18
申请人： Minobu Yazawa , Natsuko Matsuo
发明人： Minobu Yazawa , Natsuko Matsuo
IPC分类号： G06F7/38 , G06F7/50 , G06F7/505 , G06F7/507 , G06F7/508 , G06F7/509 , G06F11/00
CPC分类号： G06F7/509 , G06F7/505 , G06F7/49921
摘要： Two input data X (7), Y (7), . . . , X (0), Y (0) are input to a plurality of full adders, and an overflow/underflow signal of each full adder is input to a full adder of a higher level. An overflow/underflow signal Co of the full adder of the most significant bit and data Y (7) are applied to an EXOR gate to obtain an exclusive OR. According to an output signal of the EXOR gate, an added output of each full adder or data Y (7) is selected by a selector, whereby a straight binary signal is output.
摘要翻译：两个输入数据X（7），Y（7），。。。，X（0），Y（0）被输入到多个全加器，并且每个全加器的溢出/下溢信号被输入到较高电平的全加器。最高有效位的全加器的溢出/下溢信号Co和数据Y（7）被施加到EXOR门以获得异或。根据EXOR门的输出信号，通过选择器选择每个全加器或数据Y（7）的相加输出，由此输出直的二进制信号。

3. 发明授权

US5339344A Counter device and method of operating the same 失效
标题翻译：计数器装置及其操作方法
公开(公告)号：US5339344A
公开(公告)日：1994-08-16
申请号：US102327
申请日：1993-08-05
申请人： Masatoshi Kimura , Minobu Yazawa
发明人： Masatoshi Kimura , Minobu Yazawa
IPC分类号： G05B19/05 , H03K21/38 , H03K23/66 , G11C8/00
CPC分类号： H03K23/665 , H03K21/38
摘要： A counter device having a jumping function includes a counter circuit for counting clock pulses, a circuit for setting a jump starting count, a circuit for setting the number of bits to be jumped, a detecting circuit for detecting equality/unequality between a count of the counter circuit and the Jump starting count as set, and a circuit for modifying the count of the counter circuit by the number of bits to be jumped in response to equality detection by the detecting circuit. The modifying circuit varies the count in the same direction as a direction of variation of the count provided by the counter circuit. This construction realizes a counting function which jumps a desired count or counts from a selected count.
摘要翻译：具有跳跃功能的计数器装置包括用于计数时钟脉冲的计数器电路，用于设置跳转开始计数的电路，用于设置要跳转的位数的电路，检测电路，用于检测计数器的计数之间的相等/不等计数器电路和跳转开始计数设置，以及用于响应于检测电路的相等检测而将计数器电路的计数改变为要跳转的位数的电路。修改电路使计数与计数器电路提供的计数的变化方向相同的方向变化。这种结构实现了从所选计数中跳出期望计数或计数的计数功能。

4. 发明授权

US5317312A Analog-to-digital converter of an annular configuration 失效
标题翻译：具有环形配置的模数转换器
公开(公告)号：US5317312A
公开(公告)日：1994-05-31
申请号：US990488
申请日：1992-12-14
申请人： Hiroyuki Kouno , Minobu Yazawa , Toshio Kumamoto
发明人： Hiroyuki Kouno , Minobu Yazawa , Toshio Kumamoto
IPC分类号： H03M1/34 , H03M1/36
CPC分类号： H03M1/365
摘要： An A/D converter main body is formed in the form of an annulus with a wiring region set as its center, and a ladder resistor array for dividing an input reference voltage and an analog signal line for applying an input analog signal to each comparator in the A/D converter are formed in the form of an annulus with the wiring region set as a center. Wirings from terminals are once concentrated into the wiring region by an input/output line group and then distributed therefrom to circuit elements. Since the ladder resistor array is formed in a circular form, resistance values are less liable to change as compared to the case where the ladder resistor array is bent, resulting in a higher precision of reference voltages for comparison. Further, wiring lengths for control signals to be applied to the circuit elements are made equal, and there is no fear of line delays in the control signals.
摘要翻译： A / D转换器主体形成为以布线区域为中心的环形的形式，以及用于分割输入参考电压的梯形电阻阵列和用于将输入的模拟信号施加到每个比较器的模拟信号线 A / D转换器形成为以布线区域为中心的环形的形式。来自端子的布线一旦通过输入/输出线组集中到布线区域中，然后从电缆元件分布。由于梯形电阻器阵列形成为圆形形式，所以与梯形电阻器阵列弯曲的情况相比，电阻值不易变化，因此比较了较高的基准电压精度。此外，使施加到电路元件的控制信号的布线长度相等，并且不必担心控制信号中的线路延迟。

5. 发明授权

US06359660B1 Semiconductor integrated circuit for converting macro-block data into raster data which is adaptable to various formats 失效
标题翻译：用于将宏块数据转换成适用于各种格式的光栅数据的半导体集成电路
公开(公告)号：US06359660B1
公开(公告)日：2002-03-19
申请号：US08914192
申请日：1997-08-19
申请人： Natsuko Matsuo , Shiro Hosotani , Minobu Yazawa
发明人： Natsuko Matsuo , Shiro Hosotani , Minobu Yazawa
IPC分类号： H04N701
CPC分类号： H04N19/85 , H04N19/423 , H04N19/61
摘要： A block to raster converting circuit which is adaptable to all formats with a single circuit is realized. Macro-block data is mapped into a frame memory (13) on the basis of a particular format whose data size (X) in the horizontal direction provides a max condition. When writing, for each macro-block row (MBRi), the address of the first data in the initial macro-block (IMBi) is specified, on the basis of which address the column and row addresses are regularly switched according to the data array in the macro-block (MB). When reading, for each macro-block row (MBRi), the address of the initial data is specified, on the basis of which address the row address is switched every time data in each horizontal line in the macro-block row (MBRi) has been read and every time data at a turn of the column address in the frame memory (13) has been read. The column address is sequentially switched.
摘要翻译：实现了适用于单个电路的所有格式的块到光栅转换电路。基于在水平方向上的数据大小（X）提供最大条件的特定格式，将宏块数据映射到帧存储器（13）。当写入时，对于每个宏块行（MBRi），指定初始宏块（IMBi）中第一个数据的地址，根据哪个地址根据数据阵列定期切换列和行地址在宏块（MB）中。当读取每个宏块行（MBRi）时，指定初始数据的地址，根据宏块行（MBRi）中的每个水平行中的每个数据的哪个地址切换行地址的地址并且每当读取帧存储器（13）中的列地址的转动时的每一次数据。列地址被顺序切换。

6. 发明授权

US6157739A Displaying format converter for digitally encoded video signal data 失效
标题翻译：显示用于数字编码视频信号数据的格式转换器
公开(公告)号：US6157739A
公开(公告)日：2000-12-05
申请号：US956368
申请日：1997-10-23
申请人： Minobu Yazawa , Shiro Hosotani , Natsuko Matsuo
发明人： Minobu Yazawa , Shiro Hosotani , Natsuko Matsuo
IPC分类号： H04N5/46 , H04N7/01 , H04N19/00 , H04N19/423 , H04N19/44 , H04N19/625 , H04N19/85 , G06K9/36 , H04N5/91 , H04N11/20
CPC分类号： H04N7/01 , H04N19/423 , H04N19/427 , H04N19/61
摘要： A decoder for converting packet data into raster data is provided. The packet data includes data about a picture-compressed video signal and data about a picture format including a picture rate. The decoder comprising a first processing means, second processing means and a storage means. The first processing means converts the packet data into intermediate data such that picture compression is eliminated from the picture-compressed video signal and outputs the intermediate data. The second processing means receives the intermediate data from the first processing means and processes the intermediate data to output raster data for one frame at a frame frequency. The storage means stores the intermediate data for processing the intermediate data in the second processing means. The second processing means writes the intermediate data into the storage means at a frequency related to the picture rate and reads the raster data for one frame from the storage means at the frequency equal to the frame frequency.
摘要翻译：提供了一种用于将分组数据转换为光栅数据的解码器。分组数据包括关于图像压缩视频信号的数据和关于包括图像速率的图像格式的数据。解码器包括第一处理装置，第二处理装置和存储装置。第一处理装置将分组数据转换成中间数据，使得从图像压缩视频信号中消除图像压缩并输出中间数据。第二处理装置从第一处理装置接收中间数据，并处理中间数据，以帧频率输出一帧的光栅数据。存储装置将用于处理中间数据的中间数据存储在第二处理装置中。第二处理装置以与图像速率相关的频率将中间数据写入存储装置，并以等于帧频的频率从存储装置读取一帧的光栅数据。

7. 发明授权

US5652728A Dynamic memory 失效
标题翻译：动态内存
公开(公告)号：US5652728A
公开(公告)日：1997-07-29
申请号：US524930
申请日：1995-09-08
申请人： Shiro Hosotani , Minobu Yazawa , Kazuya Yamanaka
发明人： Shiro Hosotani , Minobu Yazawa , Kazuya Yamanaka
IPC分类号： G11C11/405 , G11C7/00 , G11C11/401 , G11C11/4099
CPC分类号： G11C11/4099
摘要： Dummy information of a third level, which is between first and second levels written in a plurality of memory cells, is written in a dummy memory cell from a source node through transistors. Thus, a potential difference is caused between a read bit line and a dummy read bit line in reading. A potential comparison circuit indicates the level of information read from any memory cell on the basis of the comparison result as to the potentials of the dummy read bit line and the read bit line. Thus, the read rate is increased, the read operation is stabilized and increase of the chip area is suppressed.
摘要翻译：写入多个存储单元的第一级和第二级之间的第三级的虚拟信息通过晶体管从源节点写入虚拟存储单元。因此，读取中的读取位线和虚拟读取位线之间产生电位差。潜在的比较电路根据关于虚拟读取位线和读取位线的电位的比较结果来指示从任何存储器单元读取的信息的电平。因此，读取速率增加，读取操作稳定，并且抑制了芯片面积的增加。

8. 发明授权

US5828618A Line memory 失效
标题翻译：行内存
公开(公告)号：US5828618A
公开(公告)日：1998-10-27
申请号：US895908
申请日：1997-07-17
申请人： Shiro Hosotani , Minobu Yazawa
发明人： Shiro Hosotani , Minobu Yazawa
IPC分类号： G11C11/41 , G11C8/04 , G11C11/401 , G11C11/405 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/405
摘要： The function of a line memory can be achieved only with one bit line. As word lines WL.sub.j-1 and WL.sub.j are activated in this order, data has already been read out before new data is written into memory cells MC.sub.j-1,i and MC.sub.j,1. More specifically, a writing process is performed on the same memory cell after a readout process, achieving delay operation as taught in a conventional technique. Further, as both operations of a tristate buffer 11 and a D latch 13 are controlled in accordance with the readout and the writing processes, one bit line serves both as a write bit line and a read bit line.
摘要翻译：行存储器的功能只能通过一条位线实现。由于字线WLj-1和WLj以此顺序被激活，所以在将新数据写入存储单元MCj-1，i和MCj，1之前已经读出数据。更具体地说，在读出处理之后对相同的存储单元执行写入处理，实现如传统技术中所教导的延迟操作。此外，由于根据读出和写入处理来控制三态缓冲器11和D锁存器13的两个操作，所以一个位线用作写入位线和读取位线。

9. 发明授权

US5612926A Sequential access memory 失效
标题翻译：顺序访问存储器
公开(公告)号：US5612926A
公开(公告)日：1997-03-18
申请号：US529065
申请日：1995-09-15
申请人： Minobu Yazawa , Shiro Hosotani
发明人： Minobu Yazawa , Shiro Hosotani
IPC分类号： G11C7/00 , G06F5/10 , G06F5/14 , G11C8/04 , H04N5/46 , H04N5/907 , G11C8/00
CPC分类号： G06F5/14 , H04N5/907 , H04N5/46 , H04N7/0122
摘要： In an FIFO memory, a word line pointer (4) sequentially specifies word lines (8) in accordance with the first clock signal (CLK1) outputted from a clock generator (3). When the last pointer (5) outputs a last line access signal (PAS3) indicating that the last word line (8E) has been accessed, a control flag generator (2) detects that the last address has been accessed on the basis of the last line access signal (PAS3) and a clock signal (COS) in synchronization with the first clock (CLK1) and outputs a clock control signal (CCNT) in accordance with a timing of the detection. The clock generator 3 stops counting a reference clock signal (CLK0) in response to the clock control signal (CCNT). Thus, the access to a memory cell array of the FIFO memory is stopped in accordance with the number of effective pixels of inputted video signals, and thereby reduction in memory capacity and in power consumption can be achieved.
摘要翻译：在FIFO存储器中，字线指针（4）根据从时钟发生器（3）输出的第一时钟信号（CLK1）顺序地指定字线（8）。当最后一个指针（5）输出表示最后一个字线（8E）被访问的最后一行访问信号（PAS3）时，控制标志发生器（2）根据最后一个线路接入信号（PAS3）和与第一时钟（CLK1）同步的时钟信号（COS），并且根据检测的定时输出时钟控制信号（CCNT）。时钟发生器3响应时钟控制信号（CCNT）停止计数参考时钟信号（CLK0）。因此，根据输入的视频信号的有效像素的数量来停止对FIFO存储器的存储单元阵列的访问，从而可以实现存储容量的降低和功耗的降低。

10. 发明授权

US5535170A Sequential access memory that can have circuit area reduced 失效
标题翻译：可以减少电路面积的顺序存取存储器
公开(公告)号：US5535170A
公开(公告)日：1996-07-09
申请号：US439558
申请日：1995-05-11
申请人： Yukinaga Imamura , Kazuya Yamanaka , Shiro Hosotani , Minobu Yazawa
发明人： Yukinaga Imamura , Kazuya Yamanaka , Shiro Hosotani , Minobu Yazawa
IPC分类号： G06F12/04 , G06F5/10 , G11C7/00 , G11C7/10 , G11C8/04 , G11C11/401 , G11C11/405 , G11C8/00
CPC分类号： G11C7/1018 , G11C8/04
摘要： y memory blocks are connected in series. A row select signal is output to each memory block from a row address pointer corresponding to a plurality of memory circuits in one memory block. Similarly, a column select signal is output to each memory block from a column address pointer corresponding to a plurality of memory circuits in one memory block. Therefore, the same row and column select signals are applied to each memory block, whereby data is sequentially input/output for every memory block. Thus, the circuit complexity of the row and column address pointers can be reduced.
摘要翻译： y内存块串联连接。行选择信号从与一个存储器块中的多个存储器电路对应的行地址指针输出到每个存储器块。类似地，列选择信号从与一个存储器块中的多个存储器电路相对应的列地址指针输出到每个存储器块。因此，对每个存储块应用相同的行和列选择信号，从而每个存储器块依次输入/输出数据。因此，可以减少行和列地址指针的电路复杂度。

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